公开(公告)号：US20110220977A1

公开(公告)日：2011-09-15

申请号：US12760140

申请日：2010-04-14

申请人： Jae-Man Yoon ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim ,  Yong-Chul Oh

发明人： Jae-Man Yoon ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim ,  Yong-Chul Oh

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/7833

摘要： A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.

摘要翻译： 一种半导体器件，包括：形成在绝缘体上硅（SOI））衬底上的垂直立柱晶体管（VPT），所述VPT包括具有下部和上部的主体，设置在上部的源极/漏极节点 本体的上部的端部和设置在主体的下部的排水/源节点; 在侧壁和下部的上表面上连续形成的埋置位线（BBL），BBL包括金属微孔; 以及字线，其部分地包围VPT的主体的上部，其中，BBL沿着第一方向延伸，并且字线在基本上垂直于第一方向的第二方向上延伸。 偏移区域设置在字线的正下方。

公开(公告)号：US07999309B2

公开(公告)日：2011-08-16

申请号：US12385433

申请日：2009-04-08

申请人： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

摘要翻译： 在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案， 所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域 在半导体图案的上部。

公开(公告)号：US07902026B2

公开(公告)日：2011-03-08

申请号：US12314139

申请日：2008-12-04

申请人： Hyun-Woo Chung ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Hyun-Woo Chung ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76237 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching the substrate using the hard mask pattern as an etch mask, reducing a width of the preliminary active pillar to form an active pillar having a width less than that of the hard mask pattern, forming a lower source/drain region by implanting impurity ions into the substrate adjacent to the active pillar using the hard mask pattern as an ion implantation mask, and forming an upper source/drain region on the active pillar and vertically separated from the lower source/drain region.

摘要翻译： 一种制造具有垂直沟道晶体管的半导体器件的方法，所述方法包括在衬底上形成硬掩模图案，通过使用硬掩模图案作为蚀刻掩模蚀刻衬底来形成预活性柱，从而减小初步 活性柱以形成宽度小于硬掩模图案的有源柱，通过使用硬掩模图案作为离子注入掩模将杂质离子注入邻近有源柱的衬底中来形成下源极/漏极区域，以及 在有源柱上形成上部源极/漏极区域，并与下部源极/漏极区域垂直分离。

公开(公告)号：US20090250736A1

公开(公告)日：2009-10-08

申请号：US12385433

申请日：2009-04-08

申请人： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

摘要翻译： 在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案， 所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域 在半导体图案的上部。

公开(公告)号：US20090242975A1

公开(公告)日：2009-10-01

申请号：US12382898

申请日：2009-03-26

申请人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/10882 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.

摘要翻译： 垂直柱状晶体管可以包括多个下部支柱，多个上部支柱，第一绝缘部分，第二绝缘部分和字线。 多个下支柱基本上垂直于基板突出并且由多个沟槽限定。 多个下柱沿着第二方向延伸并且可以沿着基本上垂直于第二方向的第一方向彼此分离。 多个上柱可以形成在多个下支柱上。 多个上支柱具有比多个下支柱的宽度更小的宽度。 第一绝缘部件在多个下支柱中的每一个的侧壁上具有基本均匀的厚度。 第二绝缘部件可以形成在第一绝缘部分上以填充相邻的上部支柱之间的间隙。 字线可以形成在第二绝缘部分上，并且可以沿着第一方向在相邻的一对上柱的相对侧壁之间延伸。

公开(公告)号：US08247856B2

公开(公告)日：2012-08-21

申请号：US12728596

申请日：2010-03-22

申请人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L27/06

CPC分类号： H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/78

摘要： A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.

摘要翻译： 半导体器件包括第一晶体管，第二晶体管，绝缘层间图案和电容器。 第一晶体管形成在衬底的第一区域中。 第一晶体管具有从基板向上突出的柱和设置在柱的上部的杂质区。 第二晶体管形成在衬底的第二区域中。 绝缘层间图案形成在第一区域和第二区域上以覆盖第二晶体管并暴露柱的上表面。 绝缘层间图案具有比第一区域中的柱的上表面大得多的上表面。 电容器形成在柱的上部的杂质区上并与杂质区电连接。

公开(公告)号：US20110183483A1

公开(公告)日：2011-07-28

申请号：US13064628

申请日：2011-04-05

申请人： Kang-Uk Kim ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

发明人： Kang-Uk Kim ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823487 ,  H01L21/823456

摘要： In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.

摘要翻译： 在半导体器件中，半导体器件可以包括第一有源结构，第一栅极绝缘层，第一栅极电极，第一杂质区域，第二杂质区域和接触结构。 第一有源结构可以包括在衬底的第一区域中的第一下部图案和第一下部图案上的第一上部图案。 第一栅极绝缘层可以形成在第一上部图案的侧壁上。 第一栅电极可以形成在第一栅极绝缘层上。 第一杂质区域可以形成在第一下部图案中。 第二杂质区域可以形成在第一上部图案中。 接触结构可以围绕第一上部图案的上表面和上侧壁包括第二杂质区域。 因此，可以降低接触结构和第二杂质区之间的接触电阻，并且可以提高接触结构的结构稳定性。

公开(公告)号：US07943978B2

公开(公告)日：2011-05-17

申请号：US12458262

申请日：2009-07-07

申请人： Kang-Uk Kim ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

发明人： Kang-Uk Kim ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

IPC分类号： H01L29/94

CPC分类号： H01L21/823487 ,  H01L21/823456

摘要： In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.

摘要翻译： 在半导体器件中，半导体器件可以包括第一有源结构，第一栅极绝缘层，第一栅极电极，第一杂质区域，第二杂质区域和接触结构。 第一有源结构可以包括在衬底的第一区域中的第一下部图案和第一下部图案上的第一上部图案。 第一栅极绝缘层可以形成在第一上部图案的侧壁上。 第一栅电极可以形成在第一栅极绝缘层上。 第一杂质区域可以形成在第一下部图案中。 第二杂质区域可以形成在第一上部图案中。 接触结构可以围绕第一上部图案的上表面和上侧壁包括第二杂质区域。 因此，可以降低接触结构和第二杂质区之间的接触电阻，并且可以提高接触结构的结构稳定性。

公开(公告)号：US08623724B2

公开(公告)日：2014-01-07

申请号：US13547318

申请日：2012-07-12

申请人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/78

摘要： A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.

摘要翻译： 半导体器件包括第一晶体管，第二晶体管，绝缘层间图案和电容器。 第一晶体管形成在衬底的第一区域中。 第一晶体管具有从基板向上突出的柱和设置在柱的上部的杂质区。 第二晶体管形成在衬底的第二区域中。 绝缘层间图案形成在第一区域和第二区域上以覆盖第二晶体管并暴露柱的上表面。 绝缘层间图案具有比第一区域中的柱的上表面大得多的上表面。 电容器形成在柱的上部的杂质区上并与杂质区电连接。

公开(公告)号：US08409953B2

公开(公告)日：2013-04-02

申请号：US13194407

申请日：2011-07-29

申请人： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

发明人： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC分类号： H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8244

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

摘要翻译： 在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案， 所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域 在半导体图案的上部。