公开(公告)号：US07592262B2

公开(公告)日：2009-09-22

申请号：US11689508

申请日：2007-03-21

申请人： Hui-Ling Huang ,  Ming-Shing Chen ,  Nien-Chung Li ,  Li-Shiun Chen ,  Hsin Tai

发明人： Hui-Ling Huang ,  Ming-Shing Chen ,  Nien-Chung Li ,  Li-Shiun Chen ,  Hsin Tai

IPC分类号： H01L21/302

CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/32139 ,  H01L29/66636

摘要： A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

摘要翻译： 一种制造具有混合硬掩模的MOS晶体管的方法包括：在其上提供具有介电层和多晶硅层的衬底，形成具有中间硬掩模和覆盖多晶硅层上的中间硬掩模的侧壁的间隔物硬掩模的混合硬掩模 执行第一蚀刻工艺以通过混合硬掩模蚀刻多晶硅层和电介质层以形成栅极结构，执行第二蚀刻工艺以在栅极结构的两侧在衬底中形成凹槽，并且执行SEG工艺 以在每个凹部中形成外延硅层。

公开(公告)号：US20080233746A1

公开(公告)日：2008-09-25

申请号：US11689508

申请日：2007-03-21

申请人： Hui-Ling Huang ,  Ming-Shing Chen ,  Nien-Chung Li ,  Li-Shiun Chen ,  Hsin Tai

发明人： Hui-Ling Huang ,  Ming-Shing Chen ,  Nien-Chung Li ,  Li-Shiun Chen ,  Hsin Tai

IPC分类号： H01L21/302

CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/32139 ,  H01L29/66636

摘要： A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

摘要翻译： 一种制造具有混合硬掩模的MOS晶体管的方法包括：在其上提供具有介电层和多晶硅层的衬底，形成具有中间硬掩模和覆盖多晶硅层上的中间硬掩模的侧壁的间隔物硬掩模的混合硬掩模 执行第一蚀刻工艺以通过混合硬掩模蚀刻多晶硅层和电介质层以形成栅极结构，执行第二蚀刻工艺以在栅极结构的两侧在衬底中形成凹槽，并且执行SEG工艺 以在每个凹部中形成外延硅层。

公开(公告)号：US20080308868A1

公开(公告)日：2008-12-18

申请号：US11763911

申请日：2007-06-15

申请人： Rong-Tzong Wu ,  Guan-Quan Chen ,  Hsin Tai ,  Am-Tay Luy ,  Pao-An Chang

发明人： Rong-Tzong Wu ,  Guan-Quan Chen ,  Hsin Tai ,  Am-Tay Luy ,  Pao-An Chang

IPC分类号： H01L23/62 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/2255 ,  H01L29/0653 ,  H01L29/66568

摘要： A high voltage metal oxide semiconductor includes a doped substrate, two first isolation structures, a gate structure, a source region, a drain region, two second isolation structures, and two drift regions. The two first isolation structures are respectively disposed in the doped substrate. The gate structure is disposed between parts of the two first isolation structures on the doped substrate. The source region and the drain region are respectively disposed beside one side of each of the two first isolation structures in the doped substrate. The top surface of the second isolation structure is smaller than the bottom surface of the first isolation structure. The two drift regions are respectively disposed in the doped substrate, enclosing the source region and the drain region, the two first isolation structures and the second isolation structures.

摘要翻译： 高电压金属氧化物半导体包括掺杂衬底，两个第一隔离结构，栅极结构，源极区，漏极区，两个第二隔离结构和两个漂移区。 两个第一隔离结构分别设置在掺杂衬底中。 栅极结构设置在掺杂衬底上的两个第一隔离结构的部分之间。 源极区域和漏极区域分别设置在掺杂衬底中的两个第一隔离结构中的每一个的旁边。 第二隔离结构的顶表面小于第一隔离结构的底表面。 两个漂移区分别设置在掺杂衬底中，包围源极区和漏极区，两个第一隔离结构和第二隔离结构。

公开(公告)号：US20070045227A1

公开(公告)日：2007-03-01

申请号：US11162156

申请日：2005-08-31

申请人： Chih-Ning Wu ,  Hsin Tai ,  Yi-Yiing Chiang

发明人： Chih-Ning Wu ,  Hsin Tai ,  Yi-Yiing Chiang

IPC分类号： C23F1/00 ,  H01L21/302 ,  B44C1/22 ,  C03C25/68

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L21/02063

摘要： A method of stripping photoresist is provided. First, a first dielectric layer including a plurality of contact structures is provided. Then, a barrier layer is formed over the first dielectric layer. Thereafter, a second dielectric layer is formed over the barrier layer. Next, a patterned photoresist layer is formed over the second dielectric layer. Then, the patterned photoresist layer is used as a mask layer for patterning the second dielectric layer and the barrier layer to expose a portion of the contact structures. Furthermore, the patterned photoresist layer is removed by using an oxygen-free reducing gas. Since the reducing gas does not contain oxygen, the process can prevent oxide from forming on the contact structures, thereby reducing resistance of the contact structures.

摘要翻译： 提供剥离光刻胶的方法。 首先，提供包括多个接触结构的第一电介质层。 然后，在第一电介质层上形成阻挡层。 此后，在阻挡层上形成第二电介质层。 接下来，在第二电介质层上形成图案化的光致抗蚀剂层。 然后，图案化的光致抗蚀剂层用作掩模层，用于图案化第二介电层和阻挡层以暴露部分接触结构。 此外，通过使用无氧还原气体去除图案化的光致抗蚀剂层。 由于还原气体不含氧，因此能够防止在接触结构上形成氧化物，从而降低接触结构的电阻。

公开(公告)号：US20070054447A1

公开(公告)日：2007-03-08

申请号：US11221487

申请日：2005-09-07

申请人： Hsin Tai ,  Chung-Ju Lee ,  Chih-Ning Wu

发明人： Hsin Tai ,  Chung-Ju Lee ,  Chih-Ning Wu

IPC分类号： H01L21/8234 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A multi-step etching method is provided. First, a substrate including a gate over the substrate and a spacer over the gate is provided. Then, an anisotropic etching step is performed for etching a first region and a second region in the substrate at two sides of the gate. Thereafter, an isotropic etching step is performed for etching a first external region under the spacer and adjacent to the first region, and etching a second external region under the spacer and adjacent to the second region. Then, a filling step is performed for filling a material into the first region, the first external region, the second region and the second external region.

摘要翻译： 提供了多步蚀刻方法。 首先，提供包括在衬底上的栅极和栅极上的间隔物的衬底。 然后，进行各向异性蚀刻步骤，以蚀刻栅极两侧的基板中的第一区域和第二区域。 此后，进行各向同性蚀刻步骤，用于蚀刻间隔物下方的第一外部区域并与第一区域相邻，并且蚀刻间隔物下方的第二外部区域并与第二区域相邻。 然后，进行用于将材料填充到第一区域，第一外部区域，第二区域和第二外部区域中的填充步骤。

公开(公告)号：US07491615B2

公开(公告)日：2009-02-17

申请号：US11162798

申请日：2005-09-23

申请人： Chih-Ning Wu ,  Hsin Tai ,  Chung-Ju Lee ,  Wei-Tsun Shiau

发明人： Chih-Ning Wu ,  Hsin Tai ,  Chung-Ju Lee ,  Wei-Tsun Shiau

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

摘要翻译： 制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底在其上包含栅极结构; 执行蚀刻工艺以形成对应于半导体衬底内的栅极结构的两个凹部; 在半导体衬底上进行氧冲洗; 对所述半导体衬底进行清洁处理; 并且在每个用于形成源/漏区的凹槽中执行选择性外延生长（SEG）以形成外延层。

公开(公告)号：US20070072353A1

公开(公告)日：2007-03-29

申请号：US11162798

申请日：2005-09-23

申请人： Chih-Ning Wu ,  Hsin Tai ,  Chung - Ju Lee ,  Wei-Tsun Shiau

发明人： Chih-Ning Wu ,  Hsin Tai ,  Chung - Ju Lee ,  Wei-Tsun Shiau

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

摘要翻译： 制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底在其上包含栅极结构; 执行蚀刻工艺以形成对应于半导体衬底内的栅极结构的两个凹部; 在半导体衬底上进行氧冲洗; 对所述半导体衬底进行清洁处理; 并且在每个用于形成源/漏区的凹槽中执行选择性外延生长（SEG）以形成外延层。