公开(公告)号：US07338910B2

公开(公告)日：2008-03-04

申请号：US11162952

申请日：2005-09-29

Applicant: Chung-Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

Inventor： Chung-Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76834 ,  H01L21/28518 ,  H01L21/31111

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括在半导体衬底上限定电极; 在所述电极的至少一个侧壁上形成间隔物; 在所述半导体衬底上使用所述间隔件作为掩模进行处理操作，并在所述半导体衬底和所述电极的顶部或表面上形成材料层; 并且通过在100℃至150℃的温度范围内进行湿蚀刻工艺的步骤去除间隔物，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。 关于另一方面，还公开了一种去除间隔物的方法。 该方法包括在100℃至150℃范围内的温度下进行湿蚀刻工艺，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。

公开(公告)号：US20070075379A1

公开(公告)日：2007-04-05

申请号：US11380212

申请日：2006-04-26

Applicant: Chih-Ning Wu ,  Chung - Ju Lee ,  Wei-Tsun Shiau

Inventor： Chih-Ning Wu ,  Chung - Ju Lee ,  Wei-Tsun Shiau

IPC: H01L21/20 ,  H01L29/76

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

Abstract: A metal-oxide-semiconductor transistor device is disclosed, in which, a silicon nitride spacer has been formed but is removed after an ion implantation process to form a source/drain region and a salicide process to form a metal silicide layer on the surface of the source/drain region and the gate electrode are performed. The metal silicide layer comprises silicon, nickel and at least one metal selected from a group consisting of iridium, iron, cobalt, platinum, palladium, molybdenum, and tantalum; therefore, when the silicon nitride spacer is removed by etching, the metal silicide layer is not damaged.

Abstract translation: 公开了一种金属氧化物半导体晶体管器件，其中已经形成了氮化硅间隔物，但是在离子注入工艺之后被去除以形成源极/漏极区域和自对准硅化物工艺以在其表面上形成金属硅化物层 源极/漏极区域和栅极电极。 金属硅化物层包括硅，镍和选自铱，铁，钴，铂，钯，钼和钽中的至少一种金属; 因此，当通过蚀刻除去氮化硅间隔物时，金属硅化物层不被损坏。

公开(公告)号：US20070072402A1

公开(公告)日：2007-03-29

申请号：US11162952

申请日：2005-09-29

Applicant: Chung - Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

Inventor： Chung - Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/28518 ,  H01L21/31111

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括在半导体衬底上限定电极; 在所述电极的至少一个侧壁上形成间隔物; 在所述半导体衬底上使用所述间隔件作为掩模进行处理操作，并在所述半导体衬底和所述电极的顶部或表面上形成材料层; 并且通过在100℃至150℃的温度范围内进行湿蚀刻工艺的步骤去除间隔物，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。 关于另一方面，还公开了一种去除间隔物的方法。 该方法包括在100℃至150℃范围内的温度下进行湿蚀刻工艺，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。

公开(公告)号：US20070045227A1

公开(公告)日：2007-03-01

申请号：US11162156

申请日：2005-08-31

Applicant: Chih-Ning Wu ,  Hsin Tai ,  Yi-Yiing Chiang

Inventor： Chih-Ning Wu ,  Hsin Tai ,  Yi-Yiing Chiang

IPC: C23F1/00 ,  H01L21/302 ,  B44C1/22 ,  C03C25/68

CPC classification number: H01L21/31138 ,  G03F7/427 ,  H01L21/02063

Abstract: A method of stripping photoresist is provided. First, a first dielectric layer including a plurality of contact structures is provided. Then, a barrier layer is formed over the first dielectric layer. Thereafter, a second dielectric layer is formed over the barrier layer. Next, a patterned photoresist layer is formed over the second dielectric layer. Then, the patterned photoresist layer is used as a mask layer for patterning the second dielectric layer and the barrier layer to expose a portion of the contact structures. Furthermore, the patterned photoresist layer is removed by using an oxygen-free reducing gas. Since the reducing gas does not contain oxygen, the process can prevent oxide from forming on the contact structures, thereby reducing resistance of the contact structures.

Abstract translation: 提供剥离光刻胶的方法。 首先，提供包括多个接触结构的第一电介质层。 然后，在第一电介质层上形成阻挡层。 此后，在阻挡层上形成第二电介质层。 接下来，在第二电介质层上形成图案化的光致抗蚀剂层。 然后，图案化的光致抗蚀剂层用作掩模层，用于图案化第二介电层和阻挡层以暴露部分接触结构。 此外，通过使用无氧还原气体去除图案化的光致抗蚀剂层。 由于还原气体不含氧，因此能够防止在接触结构上形成氧化物，从而降低接触结构的电阻。

公开(公告)号：US20050239286A1

公开(公告)日：2005-10-27

申请号：US10904151

申请日：2004-10-27

Applicant: Chih-Ning Wu ,  Wen-Liang Lien ,  Charlie Lee ,  Meiling Li

Inventor： Chih-Ning Wu ,  Wen-Liang Lien ,  Charlie Lee ,  Meiling Li

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/02063 ,  H01L21/31138 ,  H01L21/76811

Abstract: A two-step stripping method for removing via photoresist during the fabrication of trench-first partial-via dual damascene features is disclosed. In the first cleaning step, inert gas (He, Ar, N2)/fluorocarbon plasma is used to contact the remaining “Via Photo” for a short time period not exceeding 20 seconds. Thereafter, in the second cleaning step, a reducing plasma is used to completely strip the remaining “Via Photo”, thereby preventing the low-k or ultra low-k carbon-containing dielectric layer from potential carbon depletion.

Abstract translation: 公开了在制造沟槽首先部分通孔双镶嵌特征期间通过光致抗蚀剂去除的两步剥离方法。 在第一清洗步骤中，使用惰性气体（He，Ar，N 2 N 2）/氟碳等离子体与剩余的“通孔照片”接触不超过20秒的短时间。 此后，在第二清洗步骤中，使用还原等离子体来完全剥离剩余的“通孔照片”，从而防止低k或超低k含碳介质层潜在的碳消耗。

公开(公告)号：US07595234B2

公开(公告)日：2009-09-29

申请号：US11532100

申请日：2006-09-15

Applicant: Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

Inventor： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Abstract translation: 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US20080286976A1

公开(公告)日：2008-11-20

申请号：US12138428

申请日：2008-06-13

Applicant: Cheng-Kuen Chen ,  Chih-Ning Wu ,  Wei-Tsun Shiau ,  Wen-Fu Yu

Inventor： Cheng-Kuen Chen ,  Chih-Ning Wu ,  Wei-Tsun Shiau ,  Wen-Fu Yu

IPC: H01L21/461

CPC classification number: H01L29/66507 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/32134 ,  H01L21/32137 ,  H01L29/66545

Abstract: A method of removing a metal suicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.

Abstract translation: 公开了一种在半导体制造工艺中去除栅电极上的金属硅化物层的方法，其中已经形成了栅极，金属硅化物层，间隔物，氮化硅覆盖层和电介质层。 该方法包括使用氮化硅盖层作为抛光停止层进行化学机械抛光工艺以抛光电介质层，以在栅电极上露出氮化硅覆盖层; 去除暴露的氮化硅覆盖层以暴露金属硅化物层; 并执行第一蚀刻工艺以去除栅电极上的金属硅化物层。

公开(公告)号：US20070066041A1

公开(公告)日：2007-03-22

申请号：US11532100

申请日：2006-09-15

Applicant: Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

Inventor： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC: H01L21/4763

CPC classification number: H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Abstract translation: 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US06780761B1

公开(公告)日：2004-08-24

申请号：US10604771

申请日：2003-08-15

Applicant: Chih-Ning Wu ,  Ming-Hsing Liu ,  Hsiao-Pang Chou ,  Ching-Piao Lin ,  Pei-Jen Wang

Inventor： Chih-Ning Wu ,  Ming-Hsing Liu ,  Hsiao-Pang Chou ,  Ching-Piao Lin ,  Pei-Jen Wang

IPC: H01L214763

CPC classification number: H01L21/76831 ,  H01L21/76808 ,  H01L21/76826 ,  H01L2221/1031

Abstract: The present invention pertains to a via-first dual damascene process. A semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate is provided. The dielectric layer has a via opening exposing the conductive structure. The via opening is filled with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer. The GFP layer is etched back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening. A surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer is then carried out, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way.

Abstract translation: 本发明涉及一种通孔 - 第一双镶嵌工艺。 提供了在半导体衬底上具有导电结构和电介质层的半导体衬底。 电介质层具有暴露导电结构的通路孔。 通孔开口填充间隙填充聚合物，以在介电层上形成间隙填充聚合物（GFP）层。 将GFP层回蚀刻到预定深度，使得GFP层的暴露表面低于介电层的表面以形成凹陷，从而暴露通孔开口的侧壁部分。 然后进行用于改变侧壁和GFP层的暴露表面的表面性质的表面处理，从而防止随后的深UV光致抗蚀剂以化学或物理方式与GFP层的侧壁或暴露表面相互作用 。

公开(公告)号：US06635565B2

公开(公告)日：2003-10-21

申请号：US09789357

申请日：2001-02-20

Applicant: Chih-Ning Wu ,  Chan-Lon Yang ,  Sun-Chieh Chien

Inventor： Chih-Ning Wu ,  Chan-Lon Yang ,  Sun-Chieh Chien

IPC: H01L214763

CPC classification number: H01L21/02074 ,  C23F1/30 ,  H01L21/02063 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76814

Abstract: A method of cleaning a dual damascene structure includes forming a first conductive layer in a substrate. A dielectric layer is formed over the substrate. A dual damascene opening is formed in the dielectric layer to expose the first conductive layer. A H2O2 based aqueous solution is used to remove polymer residues in the dual damascene opening. A temperature of the H2O2 based aqueous solution is controlled so that the first conductive layer is not corroded. A diluted HF solution or a diluted HF and HCl solution is used to remove the polymer residues. A second conductive layer is formed over the substrate to fill the dual damascene opening. A chemical mechanical polishing process is performed with the dielectric layer serving as a polishing stop to remove the second conductive layer outside the dual damascene opening. A H2O2 based aqueous solution is used to clean the hydrocarbon particulates from the chemical mechanically polishing step. A diluted HF solution or a diluted HF and HCl solution is used to remove the slurry residues, such as silicon oxide of the slurry, from the chemical mechanical polishing step.