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    MOS Devices Having Elevated Source/Drain Regions
    1.
    发明申请
    MOS Devices Having Elevated Source/Drain Regions 审中-公开
    MOS器件具有升高的源/漏区域

    公开(公告)号：US20090140351A1

    公开(公告)日：2009-06-04

    申请号：US11948823

    申请日：2007-11-30

    申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

    发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

    IPC分类号： H01L29/78

    CPC分类号： H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

    摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

    Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions
    2.
    发明申请
    Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions 有权
    形成与浅沟槽隔离区侧壁相邻的嵌入式电介质层

    公开(公告)号：US20090045411A1

    公开(公告)日：2009-02-19

    申请号：US11839352

    申请日：2007-08-15

    申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L29/24 ,  H01L29/778

    CPC分类号： H01L29/7833 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

    摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底; 绝缘区域，其从所述半导体衬底的大致顶表面延伸到所述半导体衬底中; 邻近所述绝缘区域的嵌入式电介质间隔件，其中所述嵌入式电介质间隔件的底部邻接所述半导体衬底; 以及邻接在顶部边缘并且在嵌入的电介质间隔物的侧壁上延伸的半导体材料。

    Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions
    3.
    发明授权
    Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions 有权
    形成与浅沟槽隔离区域的侧壁相邻的嵌入电介质层

    公开(公告)号：US07928474B2

    公开(公告)日：2011-04-19

    申请号：US11839352

    申请日：2007-08-15

    申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/02

    CPC分类号： H01L29/7833 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

    摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底; 绝缘区域，其从所述半导体衬底的大致顶表面延伸到所述半导体衬底中; 邻近所述绝缘区域的嵌入式电介质间隔件，其中所述嵌入式电介质间隔件的底部邻接所述半导体衬底; 以及邻接在顶部边缘并且在嵌入的电介质间隔物的侧壁上延伸的半导体材料。

    Body-tied, strained-channel multi-gate device and methods of manufacturing same
    4.
    发明申请
    Body-tied, strained-channel multi-gate device and methods of manufacturing same 有权
    身体束紧，通道多栅极装置及其制造方法

    公开(公告)号：US20080006908A1

    公开(公告)日：2008-01-10

    申请号：US11483906

    申请日：2006-07-10

    申请人： Hong-Nien Lin ,  Horng-Chih Lin ,  Tiao-Yuan Huang

    发明人： Hong-Nien Lin ,  Horng-Chih Lin ,  Tiao-Yuan Huang

    IPC分类号： H01L29/06 ,  H01L31/00

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/7851 ,  H01L29/78687

    摘要： A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

    摘要翻译： 公开了鳍FET或其他多栅极晶体管。 晶体管包括具有第一晶格常数的半导体衬底和从半导体衬底延伸的半导体鳍片。 翅片具有与第一晶格常数不同的第二晶格常数以及顶表面和两个相对的侧表面。 晶体管还包括覆盖所述顶表面和所述两个相对侧表面的至少一部分的栅极电介质，以及覆盖所述栅极电介质的至少一部分的栅电极。 所得到的通道具有由翅片和衬底之间的晶格失配引起的应变。 可以通过选择相应的材料来调节该应变。