利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.028 秒)

    Phase changeable memory cell array region and method of forming the same
    3.
    发明授权
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US07638787B2

    公开(公告)日：2009-12-29

    申请号：US11581012

    申请日：2006-10-16

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L29/02 ,  G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME
    4.
    发明申请
    PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME 有权
    相变记忆体区域及其形成方法

    公开(公告)号：US20100055831A1

    公开(公告)日：2010-03-04

    申请号：US12617782

    申请日：2009-11-13

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/06

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase changeable memory cell array region and method of forming the same
    6.
    发明申请
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US20070111440A1

    公开(公告)日：2007-05-17

    申请号：US11581012

    申请日：2006-10-16

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/94

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase change memory device and method of fabricating the same
    7.
    发明授权
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07767568B2

    公开(公告)日：2010-08-03

    申请号：US11905244

    申请日：2007-09-28

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

    摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

    摘要翻译： 提供了一种相变存储器件及其制造方法。 具有第一表面的第一电极设置在基板上。 具有与第一表面不同的第二表面的第二电极在基板上。 第二电极可以与第一电极间隔开。 可以对应于第一电极形成第三电极。 可以对应于第二电极形成第四电极。 可以在第一表面和第三电极之间插入第一相变图案。 可以在第二表面和第四电极之间插入第二相变图案。 第一和第二相变图案的上表面可以在同一平面上。

    Phase changeable memory cell array region and method of forming the same
    9.
    发明授权
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US08039298B2

    公开(公告)日：2011-10-18

    申请号：US12617782

    申请日：2009-11-13

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/06 ,  H01L21/00 ,  G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase-changeable memory device and method of manufacturing the same
    10.
    发明授权
    Phase-changeable memory device and method of manufacturing the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07563639B2

    公开(公告)日：2009-07-21

    申请号：US11733131

    申请日：2007-04-09

    申请人： Hee-Ju Shin ,  Jong-Chan Shin ,  Soon-Oh Park ,  Hyeong-Geun An ,  Han-Bong Ko

    发明人： Hee-Ju Shin ,  Jong-Chan Shin ,  Soon-Oh Park ,  Hyeong-Geun An ,  Han-Bong Ko

    IPC分类号： H01L21/06

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

    摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.

    摘要翻译： 在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。 绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。 第一插头形成在第一开口中。 将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。 包括相变材料的第二插头形成在第二开口中。 导线和上电极分别形成在第一插头和第二插头上。