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    Hierarchical memory updating system
    1.
    发明授权
    Hierarchical memory updating system 失效
    分层记忆更新系统

    公开(公告)号：US3588839A

    公开(公告)日：1971-06-28

    申请号：US3588839D

    申请日：1969-01-15

    Applicant: IBM

    Inventor： BELADY LASZLO A ,  KUEHNER CARL J ,  LEHMAN MEIR M ,  RANDELL BRIAN

    IPC: G06F12/08 ,  G11C9/00 ,  G11C7/00

    CPC classification number: G06F12/0804

    Abstract: A COMPUTER MEMORY SYSTEM IN WHICH THE DATA IS TRANSFERRED BETWEEN HIGH-SPEED LOCAL STORAGE AND ONE OR MORE LEVELS OF A LARGER LOW SPEED STORAGE WHEREIN ALTERED DATA IS REWRITTEN IN HIGH-SPEED STORAGE IMMEDIATELY AND IN THE LOWSPEED STORAGE ON A CYCLE STEALING BASIS. CONTROLS ARE PROVIDED SO THAT WHEN A SMALL SEGMENT OF DATA IN A PARTICULAR BLOCK OR PAGE IN HIGH-SPEED STORE IS ALTERED AND INDICATOR IS SET. WHEN MEMORY BUSS TIME IS AVAILABLE TO THE LOW SPEED OR BACKUP STORE THESE INDICATORS WILL BE CHECKED AND WORDS OR LINES REWRITTEN IN SAID BACKUP STORE AS LONG AS A HIGHER PRIORITY JOB IS NOT ENCOUNTERED. WHEN IT IS DESIRED TO REPLACE A COMPLETE PAGE IN HIGH-SPEED STORAGE, INDICATORS FOR THAT PAGE ARE CHECKED AND ALL ALTERED WORDS ARE REWRITTEN IMMEDIATEDLY IN THE BACKUP STORE ON A HIGH PRIORITY BASIS AFTER WHICH THE PAGE IN THE HIGH-SPEED STORE MAY BE OVERWRITTER WITH NEW DATA FROM THE BACKUP STORE.

    Arrangement for effecting vector mode operation in multiprocessing systems
    3.
    发明授权
    Arrangement for effecting vector mode operation in multiprocessing systems 失效
    用于在多处理系统中影响矢量模式运行的布置

    公开(公告)号：US3560934A

    公开(公告)日：1971-02-02

    申请号：US3560934D

    申请日：1969-06-10

    Applicant: IBM

    Inventor： ERNST HENRY A ,  LEHMAN MEIR M ,  ROSENFELD JACK L ,  SCHLAEPPI HANS P

    IPC: G06F9/46 ,  G06F15/80 ,  G06F9/18 ,  G06F9/19

    CPC classification number: G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

    Abstract: A PROGRAM CONTROLLED TRANSISTION OF THE MODE OF OPERATION OF A MULTIPROCESSOR SYSTEM, FROM THE NORMAL MULTIPROCESSING MODE (IDEPENDENT EXECUTION OF DISTINCT INSTRUCTION SEQUENCES OF TASKS BY A PLURALITY OF PROCESSORS) TO THE VECTOR MODE (SYNCHRONOUS EXECUTION OF IDENTICAL INSTRUCTION SEQUENCES OR TASK BY A PLURALITY OF PROCESSORS) IS EFFECTED BY THE EXECUTIION OF A SPECIAL INSTRUCTION BY ONE OF THE PROCESSORS ENGAGED IN A MULTIPROCESSING TASK, WHICH THEREBY BECOMES THE SO-CALLED ORIGINATING PROCESSOR OF A VECTOR TASK. IN EXECUTING THIS SPECIAL INSTRUCTION, THE ORIGINATING PROCESSOR ACQUIRES CONTROL OVER A SPECIFIED NUMBER OF THE OTHER PROCESSORS THAT HAVE SO FAR BEEN EXECUTING INDEPENDENT TASK, CAUSING THEM TO INTERRUPT THE TASKS THEY ARE ENGAGED IN, AND THEN TO PARTICIPATE IN THE INCIPIENT VECTOR TASK. IN A SET OF PROCESSORS PARTICIPATING IN VECTOR TASK, THE ORIGINATING PROCESSOR ALONE FETCHES INSTRUCTIONS FROM STORAGE, DISTRIBUTING THEM TO THE OTHER PARTICIPATING PROCESSORS. THE INSTRUCTION SEQUENCING MECHANISM OF EACH ONE OF THE OTHER PARTICIPATING PROCESSORS, WHILE REQUIRED IN THE NORMAL MULTIPROCESSING MODE, IS DISABLED FOR AS LONG AS THAT PROCESSOR CONTINUES IN THE VECTOR MODE. THE ADDRESSING AND INDEXING MECHANISMS OF ALL PARTICIPATING PROCESSORS REMAIN EFFECTIVE IN THE VECTOR MODE, SO THAT EACH OF THE PROCESSORS CAN FETCH DATA WORDS FROM STORAGE FOR ITS OWN USE. HOWEVER, DATA FETCHING BY ALL PARTICIPATING PROCESSORS IS CYNCHRONIZED BY THE ORIGINATING PROCESSOR. IN ADDITION, SPECIAL INSTRUCTIONS INTENDED FOR USE IN VECTOR TASKS ONLY ENABLE THE ORIGINATING PROCESSOR TO FETCH INDIVIDUAL DATA WORDS, COPIES OF WHICH THEN BEING DISTRIBUTED TO ALL PARTICIPATING PROCESSORS. ANOTHER SPECIAL INSTRUCTION IN THE VECTOR TASKS EFFECTS THE TERMINATION OF THE VECTOR MODE OF OPERATION, CAUSING THE ORIGINATING PROCESSOR TO RELINQUISH CONTROL OVER THE OTHER PARTICIPATING PROCESSORS, WHICH THEREBY BECOME AVAILABLE FOR REASSIGNMENT TO INDEPENDENT TASKS AS MAY CURRENTLY BE ON RECORD ON THE TASK QUE. THEREAFTER, THE ORIGINATING PROCESSOR CONTINUES THE EXECUTION OF ITS PROGRAM IN THE NORMAL MODE OF OPERATION.

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