中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.013 seconds)

    Interruption and interlock arrangement
    1.
    发明授权
    Interruption and interlock arrangement 失效
    中断和互锁安排

    公开(公告)号：US3573736A

    公开(公告)日：1971-04-06

    申请号：US3573736D

    申请日：1968-01-15

    Applicant: IBM

    Inventor： SCHLAEPPI HANS P

    IPC: G06F9/46 ,  G06F9/18

    CPC classification number: G06F9/52

    Abstract: A program control and interlock arrangement is shown wherein a chosen state of a given number of flag bits associated with data words processed by a first program are used to selectively activate one of several other programs whenever the first program encounters a data word in such chosen state, and which also permits in a multiprogrammed and/or multiprocessing system, the locking out of designated data sets from access by a second processor or process while it is still being accessed by a first processor. The signals which control the aforementioned locking out function are provided by the same data flag bits as those that control the activating of the above-mentioned other programs. These same flag bits may be employed to set and reset the interlock signals as appropriate for the lockout function to provide the mutual interlocking required to protect several concurrent processes from operating on the same data set.

    Arrangement for effecting vector mode operation in multiprocessing systems
    4.
    发明授权
    Arrangement for effecting vector mode operation in multiprocessing systems 失效
    用于在多处理系统中影响矢量模式运行的布置

    公开(公告)号：US3560934A

    公开(公告)日：1971-02-02

    申请号：US3560934D

    申请日：1969-06-10

    Applicant: IBM

    Inventor： ERNST HENRY A ,  LEHMAN MEIR M ,  ROSENFELD JACK L ,  SCHLAEPPI HANS P

    IPC: G06F9/46 ,  G06F15/80 ,  G06F9/18 ,  G06F9/19

    CPC classification number: G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

    Abstract: A PROGRAM CONTROLLED TRANSISTION OF THE MODE OF OPERATION OF A MULTIPROCESSOR SYSTEM, FROM THE NORMAL MULTIPROCESSING MODE (IDEPENDENT EXECUTION OF DISTINCT INSTRUCTION SEQUENCES OF TASKS BY A PLURALITY OF PROCESSORS) TO THE VECTOR MODE (SYNCHRONOUS EXECUTION OF IDENTICAL INSTRUCTION SEQUENCES OR TASK BY A PLURALITY OF PROCESSORS) IS EFFECTED BY THE EXECUTIION OF A SPECIAL INSTRUCTION BY ONE OF THE PROCESSORS ENGAGED IN A MULTIPROCESSING TASK, WHICH THEREBY BECOMES THE SO-CALLED ORIGINATING PROCESSOR OF A VECTOR TASK. IN EXECUTING THIS SPECIAL INSTRUCTION, THE ORIGINATING PROCESSOR ACQUIRES CONTROL OVER A SPECIFIED NUMBER OF THE OTHER PROCESSORS THAT HAVE SO FAR BEEN EXECUTING INDEPENDENT TASK, CAUSING THEM TO INTERRUPT THE TASKS THEY ARE ENGAGED IN, AND THEN TO PARTICIPATE IN THE INCIPIENT VECTOR TASK. IN A SET OF PROCESSORS PARTICIPATING IN VECTOR TASK, THE ORIGINATING PROCESSOR ALONE FETCHES INSTRUCTIONS FROM STORAGE, DISTRIBUTING THEM TO THE OTHER PARTICIPATING PROCESSORS. THE INSTRUCTION SEQUENCING MECHANISM OF EACH ONE OF THE OTHER PARTICIPATING PROCESSORS, WHILE REQUIRED IN THE NORMAL MULTIPROCESSING MODE, IS DISABLED FOR AS LONG AS THAT PROCESSOR CONTINUES IN THE VECTOR MODE. THE ADDRESSING AND INDEXING MECHANISMS OF ALL PARTICIPATING PROCESSORS REMAIN EFFECTIVE IN THE VECTOR MODE, SO THAT EACH OF THE PROCESSORS CAN FETCH DATA WORDS FROM STORAGE FOR ITS OWN USE. HOWEVER, DATA FETCHING BY ALL PARTICIPATING PROCESSORS IS CYNCHRONIZED BY THE ORIGINATING PROCESSOR. IN ADDITION, SPECIAL INSTRUCTIONS INTENDED FOR USE IN VECTOR TASKS ONLY ENABLE THE ORIGINATING PROCESSOR TO FETCH INDIVIDUAL DATA WORDS, COPIES OF WHICH THEN BEING DISTRIBUTED TO ALL PARTICIPATING PROCESSORS. ANOTHER SPECIAL INSTRUCTION IN THE VECTOR TASKS EFFECTS THE TERMINATION OF THE VECTOR MODE OF OPERATION, CAUSING THE ORIGINATING PROCESSOR TO RELINQUISH CONTROL OVER THE OTHER PARTICIPATING PROCESSORS, WHICH THEREBY BECOME AVAILABLE FOR REASSIGNMENT TO INDEPENDENT TASKS AS MAY CURRENTLY BE ON RECORD ON THE TASK QUE. THEREAFTER, THE ORIGINATING PROCESSOR CONTINUES THE EXECUTION OF ITS PROGRAM IN THE NORMAL MODE OF OPERATION.

Patent Agency Ranking