公开(公告)号：US3655999A

公开(公告)日：1972-04-11

申请号：US3655999D

申请日：1971-04-05

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED K

IPC: G11C19/28 ,  H01L27/082 ,  G11C19/00 ,  H03K3/286

CPC classification number: G11C19/28 ,  H01L27/0821

Abstract: A shift register comprises a series of half-cells with means to transfer the information stored in each half-cell to the next half-cell in the series upon the application of a clock-pulse signal. The circuit is made with just two diffusion steps, obviating the need for an isolation diffusion or a subcollector diffusion.

Abstract translation: 移位寄存器包括一系列半单元，其具有在施加时钟脉冲信号时将存储在每个半单元中的信息传送到串联中的下一个半单元的装置。 该电路只需两个扩散步骤，避免了隔离扩散或子集电极扩散的需要。

公开(公告)号：US3922565A

公开(公告)日：1975-11-25

申请号：US41958173

申请日：1973-11-28

Applicant: IBM

Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

IPC: H01L27/00 ,  H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H03K19/013 ,  H01L27/04 ,  H03K19/12 ,  H03K19/34

CPC classification number: H03K19/013 ,  H01L27/00 ,  H01L27/0214 ,  H01L27/0237 ,  H01L27/0688 ,  H01L27/0766 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/087 ,  Y10S148/096 ,  Y10S148/117

Abstract: Disclosed is a circuit showing a switching transistor whose base is connected to diodes forming the logical inputs and whose collector forms the logical output. Power supply is effected by charge carrier injection into the emitter of the switching transistor. To this end, a complementary transistor is employed, whose emitter terminal is connected to a voltage source and whose collector and base are linked with the base and the emitter of the switching transistor respectively. The collector of the switching transistor and the diodes are made up of Schottky contacts on the semiconductor zone forming the base of the switching transistor. Also disclosed is a semiconductor structure of the circuit consisting of a layered structure with a first, second, and third semiconductor layers of alternating conductivity types. The first and second layers are ohmically contacted, whereas the third layer is provided with the Schottky contacts. The second layer simultaneously forms the emitter of the switching transistor and the base of the complementary transistor whose emitter is made up of the first layer. The third layer simultaneously forms the collector of the complementary transistor and the base of the switching transistor.

Abstract translation: 公开了一种开关晶体管的电路，其基极连接到形成逻辑输入的二极管，其集电极形成逻辑输出。 电源通过电荷载流子注入开关晶体管的发射极来实现。 为此，采用互补晶体管，其发射极端子连接到电压源，其集电极和基极分别与开关晶体管的基极和发射极连接。 开关晶体管和二极管的集电极由形成开关晶体管基极的半导体区上的肖特基触点构成。 还公开了由具有交替导电类型的第一，第二和第三半导体层的分层结构组成的电路的半导体结构。 第一层和第二层被欧姆接触，而第三层设置有肖特基接触。 第二层同时形成开关晶体管的发射极和互补晶体管的基极，其发射极由第一层组成。 第三层同时形成互补晶体管的集电极和开关晶体管的基极。

公开(公告)号：US3643231A

公开(公告)日：1972-02-15

申请号：US3643231D

申请日：1970-04-20

Applicant: IBM

Inventor： LOHREY FRED H ,  WIEDMANN SIEGFRIED K

IPC: G11C15/04 ,  G11C11/40 ,  H03K3/286

CPC classification number: G11C15/04 ,  Y10S148/037 ,  Y10S148/085

Abstract: This specification discloses an associative memory storage cell having two cross-connected transistors with the word line for the cell connected to the common emitters of the two transistors and having each of the bases of the two transistors connected to the base of an input/output transistor. This emitter of each of these input/output transistors is connected to a separate bit line and the collectors of the input/output transistors are connected together and to the associative sense amplifier. To associatively search the memory, one of the bit lines is lowered. This causes the input/output transistor connected to the lowered bit line to conduct and thereby give a no-match signal to the associative sense amplifier if its base is connected to the base of the conducting one of the two cross-connected transistors and it causes that transistor to remain nonconductive and thereby give a match signal to the associative sense amplifier if it is connected to the base of the nonconducting one of the two crossconnected transistors.

Abstract translation: 本说明书公开了一种具有两个交叉连接晶体管的相关存储器存储单元，该晶体管具有用于连接到两个晶体管的公共发射极的单元的单元线，并且两个晶体管的每个基极连接到输入/输出晶体管的基极 。 这些输入/输出晶体管中的每一个的该发射极连接到单独的位线，并且输入/输出晶体管的集电极连接在一起并连接到关联读出放大器。 为了联合搜索存储器，其中一个位线被降低。 这导致连接到降低的位线的输入/输出晶体管导通，从而如果其基极连接到两个交叉连接的晶体管中的导通的基极的基极，则向相关读出放大器提供不匹配信号，并且导致 该晶体管保持不导通，从而如果连接到两个交叉连接的晶体管中的不导通的晶体管的基极，则向相关读出放大器提供匹配信号。

公开(公告)号：US3657612A

公开(公告)日：1972-04-18

申请号：US3657612D

申请日：1970-04-20

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED K

IPC: H01L21/8222 ,  H01L27/00 ,  H01L29/73 ,  H01L5/00 ,  H01L11/06 ,  H01L19/00

CPC classification number: H01L27/00 ,  H01L21/8222 ,  H01L29/73 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/151

Abstract: This specification discloses an inversely operated planar transistor with a high current gain. That is, what is described is a scheme for improving the gain of a planar transistor formed with a base region set within an emitter region and having a collector region within the base region. The higher gain is obtained by placing a heavily doped lateral junction around the periphery of the base so that the main portion of the carrier injections into the emitter occur in a vertical direction to a closely spaced, highly doped, highly conductive buried layer.

Abstract translation: 本说明书公开了具有高电流增益的反向操作的平面晶体管。 也就是说，描述了一种用于改善由在发射极区域内设置的基极区域形成且在基极区域内具有集电极区域的平面晶体管的增益的方案。 较高的增益是通过将重掺杂的横向结周围放置在基底的周边上而获得的，使得载体的主要部分注入发射极发生在垂直方向上，并与紧密间隔的高度掺杂的高导电性掩埋层发生。

公开(公告)号：US3505573A

公开(公告)日：1970-04-07

申请号：US3505573D

申请日：1968-09-30

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED K

IPC: G11C11/411 ,  H01L27/00 ,  H01L27/102 ,  H03K3/012 ,  H03K3/288 ,  H03K3/35 ,  H01L19/00

CPC classification number: H03K3/35 ,  G11C11/4113 ,  G11C11/4116 ,  H01L27/00 ,  H01L27/1025 ,  H03K3/012 ,  H03K3/288 ,  Y10S148/037 ,  Y10S148/085

公开(公告)号：US3916218A

公开(公告)日：1975-10-28

申请号：US48834474

申请日：1974-07-15

Applicant: IBM

Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

IPC: H01L21/8226 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H03K17/14 ,  H03K19/082 ,  H03K19/091 ,  H03K19/08 ,  H01L27/04 ,  H03K19/34

CPC classification number: H01L27/0821 ,  H01L27/0237 ,  H01L27/0688 ,  H01L27/0826 ,  H03K17/14 ,  H03K19/091

Abstract: The disclosure is directed to Merged Transistor Logic, or Integrated Injection Logic. More specifically, an improved monolithically integrated binary logic circuit and power supply therefor is disclosed.

Abstract translation: 本公开涉及合并晶体管逻辑或集成注入逻辑。

公开(公告)号：US3693057A

公开(公告)日：1972-09-19

申请号：US3693057D

申请日：1971-03-24

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED K

IPC: G11C11/411 ,  H01L27/07 ,  H01L29/8605 ,  H03K3/012 ,  H01L19/00

CPC classification number: H03K3/012 ,  G11C11/4116 ,  H01L27/0755 ,  H01L29/8605

Abstract: A monolithic power switching flip flop circuit comprising a pair of cross-coupled transistors, each having a ''''pinch'''' resistor formed in one common substrate. Each pinch resistor comprises a resistor and a diode connected to each other at one terminal, the second terminal of the resistor being connected to the base of a respective transistor and the other terminal of the diode being connected to the collector of said transistor through the bulk semiconductor material of the common substrate. By suitable external electrical connections, the resistor portion of each pinch resistor is connected in parallel with the diode portion of the other pinch resistor. Thus, each resistor is shunted by a diode and placed in the collector circuit of a respective transistor to form the electrical circuit equivalent of a conventional power switching flip flop utilizing minimum bulk semiconductor material.

Abstract translation: 一种单片电源开关触发器电路，包括一对交叉耦合的晶体管，每个具有形成在一个公共衬底中的“夹点”电阻器。 每个夹持电阻器包括在一个端子处彼此连接的电阻器和二极管，电阻器的第二端子连接到相应晶体管的基极，并且二极管的另一端子通过体积连接到所述晶体管的集电极 公共衬底的半导体材料。 通过适当的外部电气连接，每个夹持电阻器的电阻器部分与另一个夹持电阻器的二极管部分并联连接。 因此，每个电阻器被二极管分流并且放置在相应晶体管的集电极电路中，以形成使用最小体积半导体材料的常规功率开关触发器的等效电路。

公开(公告)号：US3676713A

公开(公告)日：1972-07-11

申请号：US3676713D

申请日：1971-04-23

Applicant: IBM

Inventor： WIEDMANN SIEGFRIED K

IPC: H03K19/013 ,  H03K19/088 ,  H03K17/04

CPC classification number: H03K19/088 ,  H03K19/013

Abstract: This specification discloses a technique of saturation control for a transistor transistor logic (TTL) circuit which is also applicable to other types of circuits. The saturation control device is a transistor whose emitter is connected to the collector of the output transistor of the TTL circuit, its collector is connected to the base of the output transistor for the TTL circuit and its base is connected through a resistive divider network between the base and collector of the input transistor for the TTL circuit. This saturation control transistor is formed in the same isolation pocket with the input transistor for the TTL circuit by providing the input transistor with an extended base region and an additional emitter diffusion which is spaced from the other emitter diffusions and the collector contact for the input transistor so that the sections of the extended base region between the additional emitter diffusion and the other emitter diffusions and between the additional emitter diffusion and the collector contact form the resistors of the divider network.