公开(公告)号：US3625781A

公开(公告)日：1971-12-07

申请号：US3625781D

申请日：1969-05-09

Applicant: IBM

Inventor： JOSHI MADHUKAR L ,  MASTERS BURTON J ,  VIVA OSVALDO R ,  YEH TSU-HSING

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/167 ,  H01L7/44

CPC classification number: H01L29/167 ,  H01L21/00 ,  H01L21/8222 ,  Y10S118/90 ,  Y10S148/037 ,  Y10S148/062 ,  Y10S148/085 ,  Y10S148/151

Abstract: A method of fabricating high-speed planar transistor structures by reducing carrier lifetime through doping with carrier lifetime killers. Gold is diffused through the front surface of the silicon structure during transistor fabrication. The gold is introduced from the vapor phase in a controlled manner so that its solid solubility in silicon is not exceeded. A simultaneous gold and base diffusion is preferred. Such a simultaneous diffusion produces a novel planar transistor structure having a gold distribution curve with an unexpected increased concentration peak in the region proximate to the basecollector junction.