公开(公告)号：US3649388A

公开(公告)日：1972-03-14

申请号：US3649388D

申请日：1968-11-04

Applicant: IBM

Inventor： JOSHI MADHUKAR L ,  PLATT ALAN ,  WAJDA EDWARD S

IPC: C23C16/44 ,  C30B31/06 ,  E04F17/02 ,  H01L21/00 ,  H01L21/22 ,  H01L21/223 ,  H01L21/306 ,  H01L7/44

CPC classification number: H01L21/223 ,  E04F17/02 ,  H01L21/00 ,  H01L21/306 ,  Y10S148/003 ,  Y10S148/04 ,  Y10S148/041 ,  Y10S148/079

Abstract: A METHOD OF CONCURRENTLY FORMING A SHALALOW, FLAT FRONT DIFFUSION LAYER AND A HIGH SURFACE IMPURITY CONCENTRATION IN A SEMICONDUCTOR WAFER, BY PREHEATING THE WAFER TO DIFFUSION TEMPERATURE IN AN ATMOSPHERE THAT WILL NOT FORM ANY FILM, SUCH AS AN OXIDE OR NITRIDE LAYER, UPON TH SURFACE OF THE SEMICONDUCTOR WAFER; CARRYING THE DIFFUSANT,

SUCH AS AS OR P, IN A CARRIER GAS SUCH AS ARGON THAT WILL NOT INTERFERE BY LAYER FORMATION WITH THE DIFFUSION; DIFFUSING THE AS OR P TO A DEPTH NOT EXCEEDING 20 MICROINCHES; AND THEN COOLING IN AN INERT ATOMSPHERE.

公开(公告)号：US3625781A

公开(公告)日：1971-12-07

申请号：US3625781D

申请日：1969-05-09

Applicant: IBM

Inventor： JOSHI MADHUKAR L ,  MASTERS BURTON J ,  VIVA OSVALDO R ,  YEH TSU-HSING

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/167 ,  H01L7/44

CPC classification number: H01L29/167 ,  H01L21/00 ,  H01L21/8222 ,  Y10S118/90 ,  Y10S148/037 ,  Y10S148/062 ,  Y10S148/085 ,  Y10S148/151

Abstract: A method of fabricating high-speed planar transistor structures by reducing carrier lifetime through doping with carrier lifetime killers. Gold is diffused through the front surface of the silicon structure during transistor fabrication. The gold is introduced from the vapor phase in a controlled manner so that its solid solubility in silicon is not exceeded. A simultaneous gold and base diffusion is preferred. Such a simultaneous diffusion produces a novel planar transistor structure having a gold distribution curve with an unexpected increased concentration peak in the region proximate to the basecollector junction.

公开(公告)号：US3865652A

公开(公告)日：1975-02-11

申请号：US40374573

申请日：1973-10-05

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J ,  JOSHI MADHUKAR L

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  H01L7/44

CPC classification number: H01L29/76866 ,  H01L21/00 ,  H01L21/823406 ,  H01L27/1057 ,  H01L29/00 ,  H01L29/1062 ,  H01L29/42396 ,  Y10S148/053 ,  Y10S148/114 ,  Y10S148/122

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

Abstract translation: 一种半导体器件，其在单个半导体本体中包含具有改善的用于存储电荷的容量的自对准场效应晶体管和电荷耦合阵列。 该器件通过在硅体表面上的二氧化硅层上沉积多晶硅和氮化硅层而形成，并且选择性地蚀刻这些层，使得合适的掺杂剂可以扩散或离子注入到下面的硅体的选定区域中以形成 在相同的半导体本体中，改进的电荷耦合阵列具有与其相关联的改进的自对准场效应晶体管。 该方法不仅导致其中在器件表面上的氧化物下面的反型层的机会大大降低的装置，而且还提供具有较薄栅极氧化物和电荷耦合阵列的自对准场效应晶体管 这增加了存储费用的能力。 这样形成的改进的阵列在操作期间还具有零间隔的耗尽区域，从而避免了在电荷耦合阵列的耗尽区域之间或内部的不期望的电中断。 因为通过使用这些薄导电层来实现零间隔，所以可以使金属相线变窄，从而在电荷转移通道中留下开口，使得该器件特别适用于成像应用。