公开(公告)号：US10128124B2

公开(公告)日：2018-11-13

申请号：US14964406

申请日：2015-12-09

Applicant: IMEC VZW

Inventor： Eddy Kunnen ,  Steven Demuynck ,  Jürgen Bömmels

IPC: H01L21/311 ,  H01L21/768

Abstract: A method is provided for blocking a portion of a longitudinal through-hole during manufacture of a semiconductor structure, comprising the steps of: forming a stack comprising a hard mask comprising at least one trench, and a first coating filling the at least one trench and coating the hard mask, wherein the first coating comprises one or more materials that can be etched selectively with respect to a second coating; etching at least one vertical via in the first coating directly above the portion of the trench in such a way as to remove the first coating over at least a fraction of the depth of the trench, filling the at least one via with the second coating material, and removing the first coating selectively with respect to the second coating from at least the one or more longitudinal through-holes in such a way as to leave in place any of the first coating present directly underneath the second coating.

公开(公告)号：US09502264B2

公开(公告)日：2016-11-22

申请号：US14827774

申请日：2015-08-17

Applicant: IMEC VZW

Inventor： Eddy Kunnen ,  Vasile Paraschiv

IPC: H01L21/302 ,  H01L21/311 ,  C01B35/06 ,  C09K13/00 ,  H01L21/768

CPC classification number: H01L21/31144 ,  C01B35/061 ,  C09K13/00 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Abstract translation: 公开了一种用于去除至少包含硅和至少氮的材料选择性的氧化物的方法，所述方法包括在反应器中提供具有包含区域的表面的结构，其中所述区域包括至少包含硅和至少氮 在所述结构上提供覆盖所述区域的至少一部分的氧化物层，以及通过蚀刻去除对所述材料选择性的所述氧化物层，从而暴露所述区域的所述至少覆盖部分的至少一部分，其中所述蚀刻完成 仅通过提供包含硼的蚀刻剂气体，由此将低于30V的电压偏压施加到该结构。

公开(公告)号：US20160049310A1

公开(公告)日：2016-02-18

申请号：US14827774

申请日：2015-08-17

Applicant: IMEC VZW

Inventor： Eddy Kunnen ,  Vasile Paraschiv

IPC: H01L21/311 ,  C09K13/00 ,  C01B35/06

CPC classification number: H01L21/31144 ,  C01B35/061 ,  C09K13/00 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Abstract translation: 公开了一种用于去除至少包含硅和至少氮的材料选择性的氧化物的方法，所述方法包括在反应器中提供具有包含区域的表面的结构，其中所述区域包括至少包含硅和至少氮 在所述结构上提供覆盖所述区域的至少一部分的氧化物层，以及通过蚀刻去除对所述材料选择性的所述氧化物层，从而暴露所述区域的所述至少覆盖部分的至少一部分，其中所述蚀刻完成 仅通过提供包含硼的蚀刻剂气体，由此将低于30V的电压偏压施加到该结构。

公开(公告)号：US10768138B2

公开(公告)日：2020-09-08

申请号：US16228092

申请日：2018-12-20

Applicant: IMEC VZW

Inventor： Koen Martens ,  Nadine Collaert ,  Eddy Kunnen ,  Simone Severi

IPC: G01N27/414

Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.

公开(公告)号：US20190195827A1

公开(公告)日：2019-06-27

申请号：US16228092

申请日：2018-12-20

Applicant: IMEC VZW

Inventor： Koen Martens ,  Nadine Collaert ,  Eddy Kunnen ,  Simone Severi

IPC: G01N27/414

CPC classification number: G01N27/4146 ,  G01N27/4145

Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.