公开(公告)号：US20240128124A1

公开(公告)日：2024-04-18

申请号：US18343467

申请日：2023-06-28

Applicant: IMEC VZW

Inventor： Sujith Subramanian

IPC: H01L21/822 ,  H01L27/12

CPC classification number: H01L21/8221 ,  H01L27/12

Abstract: A method for forming a stacked transistor device is disclosed, in which a nanosheet field-effect transistor (FET) structure and a fin FET structure are formed. The method comprises forming a first fin structure and a second fin structure from a vertical stack, wherein the second fin structure is arranged above the first fin structure, and wherein the vertical stack comprises a middle layer arranged between the first and second fin structures. The method further comprises forming, from above, a gate structure across a channel region of the second fin structure, forming, from below, a gate structure across a channel region of the first fin structure, and forming source and drain regions for the first and second fin structures.

公开(公告)号：US20230420544A1

公开(公告)日：2023-12-28

申请号：US18341196

申请日：2023-06-26

Applicant: IMEC vzw

Inventor： Hans Mertens ,  Sujith Subramanian

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L27/0924 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823807 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: In one aspect, a method of forming a semiconductor device including a plurality of stacked transistor devices having a bottom transistor device and a top transistor device can include: forming a plurality of parallel fin structures on a substrate; forming a sacrificial gate across the fin structures; forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming a bottom dummy contact layer covering the bottom source/drain bodies; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy; depositing an insulating material over the bottom dummy contact layer and the top source/drain bodies; replacing the sacrificial gate with a functional gate stack by a replacement metal gate process; patterning holes extending through the insulating material, with each hole exposing an upper surface portion of the bottom dummy contact layer; replacing the bottom dummy contact layer with one or more contact metals, which can include etching the dummy material via the holes and thereafter depositing the one or more contact metals via the holes; and etching cuts through the contact metal via the holes.

公开(公告)号：US20240206145A1

公开(公告)日：2024-06-20

申请号：US18545760

申请日：2023-12-19

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan ,  Sujith Subramanian

IPC: H10B10/00 ,  H01L23/528

CPC classification number: H10B10/125 ,  H01L23/5286

Abstract: The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.

公开(公告)号：US20230187539A1

公开(公告)日：2023-06-15

申请号：US18063859

申请日：2022-12-09

Applicant: IMEC VZW

Inventor： Sujith Subramanian ,  Hans Mertens ,  Steven Demuynck

IPC: H01L29/66 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1033 ,  H01L29/66545

Abstract: A method for forming a first transistor structure from a first channel layer and a second transistor structure from a second channel layer is disclosed. The first channel layer and the second channel layer are vertically stacked on a substrate. The method includes processing the first transistor structure from above, followed by processing the second transistor structure from the backside.

公开(公告)号：US20230187528A1

公开(公告)日：2023-06-15

申请号：US18065122

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Sujith Subramanian ,  Steven Demuynck ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66545

Abstract: The disclosed method includes forming an initial layer stack comprising a sacrificial layer of a first semiconductor material and over the sacrificial layer a channel layer of a second semiconductor material, forming a fin structures by patterning trenches in the initial layer stack, forming an anchoring structure extending across the fin structures, and while the channel layers are anchored by the anchoring structure: removing the sacrificial layers by a selective etching of the first semiconductor material, thereby forming a longitudinal cavity underneath the channel layer of each fin structure, and depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric, and subsequently recessing the at least one anchoring structure and the insulating material to a level below the cavities such that the insulating material remains in the cavities to form insulating layers underneath the channel layers of each fin structure.