公开(公告)号：US20210351275A1

公开(公告)日：2021-11-11

申请号：US17308453

申请日：2021-05-05

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Yusuke Oniki ,  Hans Mertens

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/311 ,  H01L29/66

Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

公开(公告)号：US11996459B2

公开(公告)日：2024-05-28

申请号：US17308453

申请日：2021-05-05

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Yusuke Oniki ,  Hans Mertens

IPC: H01L29/00 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/311 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

公开(公告)号：US20230420544A1

公开(公告)日：2023-12-28

申请号：US18341196

申请日：2023-06-26

Applicant: IMEC vzw

Inventor： Hans Mertens ,  Sujith Subramanian

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L27/0924 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823807 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: In one aspect, a method of forming a semiconductor device including a plurality of stacked transistor devices having a bottom transistor device and a top transistor device can include: forming a plurality of parallel fin structures on a substrate; forming a sacrificial gate across the fin structures; forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming a bottom dummy contact layer covering the bottom source/drain bodies; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy; depositing an insulating material over the bottom dummy contact layer and the top source/drain bodies; replacing the sacrificial gate with a functional gate stack by a replacement metal gate process; patterning holes extending through the insulating material, with each hole exposing an upper surface portion of the bottom dummy contact layer; replacing the bottom dummy contact layer with one or more contact metals, which can include etching the dummy material via the holes and thereafter depositing the one or more contact metals via the holes; and etching cuts through the contact metal via the holes.

公开(公告)号：US20180166558A1

公开(公告)日：2018-06-14

申请号：US15822497

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Liesbeth Witters ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

公开(公告)号：US12154832B2

公开(公告)日：2024-11-26

申请号：US17504842

申请日：2021-10-19

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens

IPC: H01L21/8238 ,  H01L27/092

Abstract: According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising: depositing a material layer over a first and second layer stack formed in a first and second device region of a substrate, respectively, each layer stack comprising a number of semiconductor channel layers and the layer stacks being separated by a trench filled with insulating material to form an insulating wall between the layer stacks and between the device regions; forming a contact partition trench in the material layer at a position above the insulating wall, and filling the contact partition trench with an insulating material to form a contact partition wall on top of the insulating wall; forming a first and a second source/drain contact trench on mutually opposite sides of the contact partition wall, the first source/drain contact trench being formed above a source/drain region in the first device region, and the second source/drain contact trench being formed above a source/drain region in the second device region, and the source/drain regions in the first and the second device region being separated by the insulating wall; and forming a first contact in the first source/drain contact trench and a second contact in the second source/drain contact trench, wherein the first and second contacts are separated by the contact partition wall.

公开(公告)号：US10361268B2

公开(公告)日：2019-07-23

申请号：US15907878

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC: H01L29/06 ,  H01L29/66 ,  B82Y40/00 ,  H01L21/8234 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L21/311

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US10269929B2

公开(公告)日：2019-04-23

申请号：US15822497

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Liesbeth Witters ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

公开(公告)号：US20180254321A1

公开(公告)日：2018-09-06

申请号：US15907878

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/0653 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823425 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US12237371B2

公开(公告)日：2025-02-25

申请号：US17476747

申请日：2021-09-16

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Eugenio Dentoni Litta

IPC: H01L29/06 ,  H01L29/786

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

公开(公告)号：US20240136225A1

公开(公告)日：2024-04-25

申请号：US18486370

申请日：2023-10-12

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.