公开(公告)号：US11367662B2

公开(公告)日：2022-06-21

申请号：US16938168

申请日：2020-07-24

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Yusuke Oniki ,  Lars-Ake Ragnarsson ,  Naoto Horiguchi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.

公开(公告)号：US11996459B2

公开(公告)日：2024-05-28

申请号：US17308453

申请日：2021-05-05

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Yusuke Oniki ,  Hans Mertens

IPC: H01L29/00 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/311 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

公开(公告)号：US20210351275A1

公开(公告)日：2021-11-11

申请号：US17308453

申请日：2021-05-05

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Yusuke Oniki ,  Hans Mertens

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/311 ,  H01L29/66

Abstract: Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

公开(公告)号：US20210028068A1

公开(公告)日：2021-01-28

申请号：US16938168

申请日：2020-07-24

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Yusuke Oniki ,  Lars-Ake Ragnarsson ,  Naoto Horiguchi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.