公开(公告)号：US20150028428A1

公开(公告)日：2015-01-29

申请号：US14341629

申请日：2014-07-25

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Han Chung Lin ,  Laura Nyns ,  Tsvetan Ivanov ,  Dennis Van Dorp

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/513 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/517

Abstract: A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.

Abstract translation: 半导体结构包括包括III-V材料的衬底和覆盖衬底的高k界面层。 界面层包括稀土铝酸盐。 本公开还涉及包括该n型FET的n型FET器件及其制造方法。

公开(公告)号：US09691872B2

公开(公告)日：2017-06-27

申请号：US14341629

申请日：2014-07-25

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Han Chung Lin ,  Laura Nyns ,  Tsvetan Ivanov ,  Dennis Van Dorp

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/20

CPC classification number: H01L29/513 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/517

Abstract: A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.

公开(公告)号：US11056376B2

公开(公告)日：2021-07-06

申请号：US16674953

申请日：2019-11-05

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Jean-Francois de Marneffe ,  Daniil Marinov ,  Han Chung Lin ,  Inge Asselberghs

IPC: H01L21/683 ,  H01L21/02 ,  H01L21/78 ,  H01L29/24 ,  H01L29/786

Abstract: In a first aspect, the present disclosure relates to a method for removing an organic sacrificial material from a 2D material, comprising: providing a target substrate having thereon the 2D material and a layer of the organic sacrificial material over the 2D material, infiltrating the organic sacrificial material with a metal or ceramic material, and removing the organic sacrificial material.

公开(公告)号：US10672894B2

公开(公告)日：2020-06-02

申请号：US16216833

申请日：2018-12-11

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Hanns Christoph Adelmann ,  Han Chung Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02

Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

公开(公告)号：US20190198638A1

公开(公告)日：2019-06-27

申请号：US16216833

申请日：2018-12-11

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Hanns Christoph Adelmann ,  Han Chung Lin

IPC: H01L29/66 ,  H01L21/02

Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.