公开(公告)号：US20240188304A1

公开(公告)日：2024-06-06

申请号：US18526150

申请日：2023-12-01

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN

Inventor： Jan Van Houdt ,  Shankha Mukherjee ,  Sergiu Clima ,  Jasper Bizindavyi

IPC: H10B53/30 ,  H01L21/28

CPC classification number: H10B53/30 ,  H01L28/60 ,  H01L29/40111

Abstract: The disclosure relates to a capacitive memory structure (10), comprising: a substrate (11); a first metallic layer (12) on the substrate; a ferroelectric material layer (13) on the first metallic layer (12); wherein the ferroelectric material layer (13) is electrically excitable to two polarization states, each polarization state representing a memory state of the capacitive memory structure (10). The capacitive memory structure (10) further comprises a second metallic layer (14) on the ferroelectric material layer (13); wherein the first metallic layer (12) and the second metallic layer (14) have different work functions.

公开(公告)号：US20230200078A1

公开(公告)日：2023-06-22

申请号：US18065335

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Mihaela Ioana Popovici ,  Jan Van Houdt ,  Amey Mahadev Walke ,  Gouri Sankar Kar ,  Jasper Bizindavyi

IPC: H10B51/00 ,  H01L29/786 ,  H01L27/12 ,  C23C16/455

CPC classification number: H01L27/11585 ,  C23C16/45536 ,  H01L27/1222 ,  H01L28/60 ,  H01L29/7869

Abstract: Example embodiments relate to ferroelectric devices. An example ferroelectric device layer structure includes a first electrode. The ferroelectric device layer structure also includes a second electrode. Additionally, the ferroelectric device layer structure includes a ferroelectric layer of hafnium zirconate (HZO). Further, the ferroelectric device layer structure includes an oxide layer of Nb2O5 or Ta2O5 arranged on the ferroelectric layer. The ferroelectric layer and the oxide layer are arranged between the first electrode and the second electrode.

公开(公告)号：US10522624B2

公开(公告)日：2019-12-31

申请号：US15824805

申请日：2017-11-28

Applicant: IMEC vzw

Inventor： Jan Van Houdt

IPC: H01L29/10 ,  H01L27/11597 ,  H01L27/11556 ,  H01L45/00 ,  H01L27/24 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of fabricating a vertical channel 3D semiconductor memory device is disclosed. In one aspect, the method comprises providing a stack of alternating layers of conductive material and dielectric material on a major surface of substrate, providing in the stack at least one trench, having sloped sidewalls sloping towards the major surface, extending at least below the lowest layer of conductive material, forming, in order, a programmable material, a channel liner, and a filler material on the sidewalls of the trench. Thereby, the method forms a memory string, and an electrode to the channel liner at opposite ends of the memory string.

公开(公告)号：US20190198080A1

公开(公告)日：2019-06-27

申请号：US16196335

申请日：2018-11-20

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot ,  Jan Van Houdt ,  Julien Ryckaert

IPC: G11C11/22 ,  H01L27/11585 ,  H01L29/78 ,  H01L29/51

CPC classification number: G11C11/223 ,  G11C11/2275 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: According to one aspect, a ferroelectric field effect transistor (FeFET) memory device and a method of programming the device is disclosed. The FeFET is configured such that a ferroelectric memory region of the FeFET is programmable by an electric field applied between a gate structure and a source region and a drain region through the ferroelectric region.

公开(公告)号：US20240015984A1

公开(公告)日：2024-01-11

申请号：US18349046

申请日：2023-07-07

Applicant: IMEC VZW

Inventor： Mihaela Ioana Popovici ,  Jasper Bizindavyi ,  Jan Van Houdt ,  Romain Delhougne

IPC: H10B53/30 ,  H10B51/30 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B53/30 ,  H10B51/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure generally relates to a ferroelectric device, and more particularly to a ferroelectric device including a layer stack. According to embodiments, the ferroelectric device comprises a first electrode and a second electrode, and the layer stack arranged between the first electrode and the second electrode. The layer stack comprises a titanium oxide layer, a doped HZO layer arranged on the titanium oxide layer, and a niobium oxide layer arranged on the doped HZO layer.

公开(公告)号：US11296117B2

公开(公告)日：2022-04-05

申请号：US17112475

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Jan Van Houdt

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11585 ,  H01L27/11578 ,  H01L27/1158

Abstract: The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

公开(公告)号：US11211404B2

公开(公告)日：2021-12-28

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: G11C11/22 ,  H01L27/1159 ,  G11C11/4096 ,  H01L27/108 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

公开(公告)号：US11211108B2

公开(公告)日：2021-12-28

申请号：US16226356

申请日：2018-12-19

Applicant: IMEC vzw

Inventor： Jan Van Houdt

IPC: G11C11/22 ,  H01L23/528 ,  H01L27/11507

Abstract: The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.

公开(公告)号：US20210175254A1

公开(公告)日：2021-06-10

申请号：US17112475

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Jan Van Houdt

IPC: H01L27/11597 ,  H01L27/1159

Abstract: The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

公开(公告)号：US10672894B2

公开(公告)日：2020-06-02

申请号：US16216833

申请日：2018-12-11

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Hanns Christoph Adelmann ,  Han Chung Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02

Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.