公开(公告)号：US10566250B2

公开(公告)日：2020-02-18

申请号：US16271626

申请日：2019-02-08

Applicant: IMEC vzw

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L29/66 ,  H01L21/8258 ,  H01L21/84 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/8252 ,  H01L27/12 ,  H01L29/423

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US10818491B2

公开(公告)日：2020-10-27

申请号：US16423274

申请日：2019-05-28

Applicant: IMEC VZW

Inventor： Ming Zhao ,  Weiming Guo

IPC: H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L29/15 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

公开(公告)号：US20180082901A1

公开(公告)日：2018-03-22

申请号：US15713417

申请日：2017-09-22

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8252 ,  H01L21/8234

CPC classification number: H01L21/8258 ,  H01L21/823487 ,  H01L21/8252 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US20190362967A1

公开(公告)日：2019-11-28

申请号：US16423274

申请日：2019-05-28

Applicant: IMEC VZW

Inventor： Ming Zhao ,  Weiming Guo

IPC: H01L21/02 ,  H01L29/15 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778 ,  H01L21/76 ,  H01L29/66

Abstract: According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

公开(公告)号：US20190244862A1

公开(公告)日：2019-08-08

申请号：US16271626

申请日：2019-02-08

Applicant: IMEC vzw

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8252 ,  H01L29/786

CPC classification number: H01L21/8258 ,  H01L21/823487 ,  H01L21/8252 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US10224250B2

公开(公告)日：2019-03-05

申请号：US15713417

申请日：2017-09-22

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L21/8258 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.