公开(公告)号：US20250098414A1

公开(公告)日：2025-03-20

申请号：US18397244

申请日：2023-12-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Haw-Tyng HUANG ,  Po-Chun YEH ,  Hsien-Yi LIAO ,  Yao-Cing HAN

IPC: H10K59/121 ,  G09G3/3233 ,  H10K59/12 ,  H10K59/124

Abstract: An all-oxide transistor structure includes a substrate having an upper surface and a first transistor disposed on the upper surface of the substrate. The first transistor includes a first drain, a first dielectric layer, a first source, at least one first opening and a first channel layer. The first drain, the first dielectric layer and the first source are disposed on the substrate along a first direction, and the first direction is parallel to a normal direction of the upper surface. The first opening passes through the first drain, the first dielectric layer and the first source along the first direction. The first channel layer, the first gate dielectric layer and the first gate are disposed in the first opening. The first gate dielectric layer is disposed on the first channel layer. The first gate is disposed on the first gate dielectric layer.

公开(公告)号：US20240145559A1

公开(公告)日：2024-05-02

申请号：US18086053

申请日：2022-12-21

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chang-Yan HSIEH ,  Po-Tsung TU ,  Jui-Chin CHEN ,  Hui-Yu CHEN ,  Po-Chun YEH

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31116 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/778

Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.

公开(公告)号：US20220359549A1

公开(公告)日：2022-11-10

申请号：US17368686

申请日：2021-07-06

Applicant: Industrial Technology Research Institute

Inventor： Yu-De LIN ,  Po-Chun YEH ,  Pei-Jer TZENG

IPC: H01L27/11507

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer.

公开(公告)号：US20250107332A1

公开(公告)日：2025-03-27

申请号：US18970364

申请日：2024-12-05

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Po-Chun YEH ,  Sih-Han LI ,  Jian-Wei SU

IPC: H10K59/121 ,  H10K59/12

Abstract: An all-oxide transistor structure includes a substrate, a first transistor, a second transistor, a third transistor and a fourth transistor. The substrate has an upper surface. The first transistor is disposed on the upper surface of the substrate. The second transistor is disposed on the upper surface of the substrate, wherein the second transistor is electrically connected to the first transistor. The third transistor is electrically connected to the second transistor and overlapped with the second transistor in a first direction, wherein the first direction is parallel to a normal direction of the upper surface of the substrate. The fourth transistor is disposed on the upper surface of the substrate, wherein the fourth transistor is electrically connected to the first transistor, the second transistor and the third transistor.

公开(公告)号：US20210242304A1

公开(公告)日：2021-08-05

申请号：US16842589

申请日：2020-04-07

Applicant: Industrial Technology Research Institute

Inventor： Yu-De LIN ,  Heng-Yuan LEE ,  Po-Chun YEH ,  Chih-Yao WANG ,  Hsin-Yun YANG

IPC: H01L49/02

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

公开(公告)号：US20210174855A1

公开(公告)日：2021-06-10

申请号：US16907101

申请日：2020-06-19

Applicant: Industrial Technology Research Institute

Inventor： Yu-De LIN ,  Heng-Yuan LEE ,  Po-Chun YEH ,  Hsin-Yun YANG

IPC: G11C11/22

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of (110) or (220), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of (110) or (220), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of (111).