公开(公告)号：USD976852S1

公开(公告)日：2023-01-31

申请号：US29738677

申请日：2020-06-18

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Designer： Sheng-Tsai Wu ,  Hsin-Han Lin ,  Yuan-Yin Lo ,  Kuo-Shu Kao ,  Tai-Jyun Yu ,  Han-Lin Wu ,  Yen-Ting Lin

公开(公告)号：US11776867B2

公开(公告)日：2023-10-03

申请号：US17839500

申请日：2022-06-14

Applicant: Industrial Technology Research Institute

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/495 ,  H01L23/373 ,  H01L23/433

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L23/3731 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/3121 ,  H01L2224/26175 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

公开(公告)号：US20220310473A1

公开(公告)日：2022-09-29

申请号：US17839500

申请日：2022-06-14

Applicant: Industrial Technology Research Institute

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/495 ,  H01L23/373 ,  H01L23/433

Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

公开(公告)号：US11387159B2

公开(公告)日：2022-07-12

申请号：US16808369

申请日：2020-03-04

Applicant: Industrial Technology Research Institute

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/31 ,  H01L23/433

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

公开(公告)号：US20190109064A1

公开(公告)日：2019-04-11

申请号：US15976886

申请日：2018-05-11

Applicant: Industrial Technology Research Institute

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/495

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.