-
公开(公告)号：US20220310473A1
公开(公告)日：2022-09-29
申请号：US17839500
申请日：2022-06-14
Applicant: Industrial Technology Research Institute
Inventor： Kuo-Shu Kao , Tao-Chih Chang , Wen-Chih Chen , Tai-Jyun Yu , Po-Kai Chiu , Yen-Ting Lin , Wei-Kuo Han
IPC: H01L23/367 , H01L23/31 , H01L23/495 , H01L23/373 , H01L23/433
Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.
-
公开(公告)号：US11387159B2
公开(公告)日：2022-07-12
申请号：US16808369
申请日：2020-03-04
Applicant: Industrial Technology Research Institute
Inventor： Kuo-Shu Kao , Tao-Chih Chang , Wen-Chih Chen , Tai-Jyun Yu , Po-Kai Chiu , Yen-Ting Lin , Wei-Kuo Han
IPC: H01L23/367 , H01L23/373 , H01L23/495 , H01L23/31 , H01L23/433
Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
-
公开(公告)号：US20190109064A1
公开(公告)日：2019-04-11
申请号：US15976886
申请日：2018-05-11
Applicant: Industrial Technology Research Institute
Inventor： Kuo-Shu Kao , Tao-Chih Chang , Wen-Chih Chen , Tai-Jyun Yu , Po-Kai Chiu , Yen-Ting Lin , Wei-Kuo Han
IPC: H01L23/367 , H01L23/31 , H01L23/373 , H01L23/495
Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
-
公开(公告)号：US09915184B2
公开(公告)日：2018-03-13
申请号：US14571118
申请日：2014-12-15
Applicant: Industrial Technology Research Institute
Inventor： Wei-Kuo Han , Chun-Kai Liu
Abstract: A waste heat exchanger may include an inner tube, an outer tube, a fin assembly and a plurality of heat electric modules The inner tube has a plurality of holes. Disposed inside the inner tube is a plurality of inlet channels and a plurality of outlet channels. The plurality of inlet channels and the plurality of outlet channels are disposed to correspond to each other. The plurality of inlet channels and the plurality of outlet channels are connected to the plurality of holes. A fluid flows through the plurality of inlets and the plurality of holes to get into the outlet channels. The outer tube is disposed outside the inner tube. The conductive assembly is positioned between the inner tube and the outer tube. The conductive assembly is disposed on an outside surface of the inner tube and an inside surface of the outer tube.
-
公开(公告)号：US20160053653A1
公开(公告)日：2016-02-25
申请号：US14571118
申请日：2014-12-15
Applicant: Industrial Technology Research Institute
Inventor： Wei-Kuo Han , Chun-Kai Liu
Abstract: A waste heat exchanger may include an inner tube, an outer tube, a fin assembly and a plurality of heat electric modules The inner tube has a plurality of holes. Disposed inside the inner tube is a plurality of inlet channels and a plurality of outlet channels. The plurality of inlet channels and the plurality of outlet channels are disposed to correspond to each other. The plurality of inlet channels and the plurality of outlet channels are connected to the plurality of holes. A fluid flows through the plurality of inlets and the plurality of holes to get into the outlet channels. The outer tube is disposed outside the inner tube. The conductive assembly is positioned between the inner tube and the outer tube. The conductive assembly is disposed on an outside surface of the inner tube and an inside surface of the outer tube.
Abstract translation: 废热交换器可以包括内管，外管，翅片组件和多个热电模块。内管具有多个孔。 设置在内管内部的是多个入口通道和多个出口通道。 多个入口通道和多个出口通道被设置成彼此对应。 多个入口通道和多个出口通道连接到多个孔。 流体流过多个入口和多个孔以进入出口通道。 外管设置在内管的外侧。 导电组件位于内管和外管之间。 导电组件设置在内管的外表面和外管的内表面上。
-
Patent Agency Ranking
6.发明授权公开(公告)号：US11239211B2
公开(公告)日：2022-02-01
申请号：US16735707
申请日：2020-01-07
Applicant: Industrial Technology Research Institute
Inventor： Wei-Kuo Han , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/48 , H01L21/44 , H05K7/00 , H01R9/00 , H01L25/07 , H01L23/498 , H01L23/528 , H01L23/00
Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.
-
公开(公告)号：US11756858B2
公开(公告)日：2023-09-12
申请号：US17140145
申请日：2021-01-04
Inventor： Wei-Kuo Han , Chia-Yen Lee , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/40
CPC classification number: H01L23/40
Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.
-
公开(公告)号：US11114387B2
公开(公告)日：2021-09-07
申请号：US16108272
申请日：2018-08-22
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jing-Yao Chang , Tao-Chih Chang , Fang-Jun Leu , Wei-Kuo Han , Kuo-Shu Kao
IPC: H01L23/00
Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.
-
公开(公告)号：US20210210409A1
公开(公告)日：2021-07-08
申请号：US17140145
申请日：2021-01-04
Inventor： Wei-Kuo Han , Chia-Yen Lee , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/40
Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.
-
公开(公告)号：US11776867B2
公开(公告)日：2023-10-03
申请号：US17839500
申请日：2022-06-14
Applicant: Industrial Technology Research Institute
Inventor： Kuo-Shu Kao , Tao-Chih Chang , Wen-Chih Chen , Tai-Jyun Yu , Po-Kai Chiu , Yen-Ting Lin , Wei-Kuo Han
IPC: H01L23/367 , H01L23/31 , H01L23/495 , H01L23/373 , H01L23/433
CPC classification number: H01L23/367 , H01L23/3157 , H01L23/3731 , H01L23/4334 , H01L23/4951 , H01L23/49531 , H01L23/49575 , H01L23/49586 , H01L23/3121 , H01L2224/26175 , H01L2224/48091 , H01L2224/48137 , H01L2224/73265 , H01L2924/181 , H01L2224/48091 , H01L2924/00014 , H01L2924/181 , H01L2924/00012
Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.017 seconds)
