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    POWER MODULE
    2.
    发明公开
    POWER MODULE 审中-公开

    公开(公告)号：US20240162114A1

    公开(公告)日：2024-05-16

    申请号：US18166496

    申请日：2023-02-09

    Applicant: Industrial Technology Research Institute

    Inventor： Shian-Chiau Chiou ,  Chun-Kai Liu ,  Po-Kai Chiu ,  Chih-Ming Tzeng ,  Yao-Shun Chen

    IPC: H01L23/427 ,  H01L23/498

    CPC classification number: H01L23/427 ,  H01L23/49894 ,  H01L24/32

    Abstract: A power module including at least one power device, an insulation thermally conductive layer, and a heat dissipation device is provided. The insulation thermally conductive layer has a patterned circuit layer. The power device is disposed on the patterned circuit layer and is electrically connected to the patterned circuit layer. The heat dissipation device includes a heat dissipation plate and a heat dissipation base. The heat dissipation plate has a first surface and a second surface opposite to each other, and the insulation thermally conductive layer is disposed on the first surface. The heat dissipation base is partially bonded to the heat dissipation plate, and a chamber is formed between the heat dissipation plate and the heat dissipation bases. The heat dissipation base has a plurality of first heat dissipation bumps located in the chamber.

    Power module
    4.
    发明授权
    Power module 有权

    公开(公告)号：US11362014B2

    公开(公告)日：2022-06-14

    申请号：US16884403

    申请日：2020-05-27

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Chun-Kai Liu ,  Yao-Shun Chen ,  Po-Kai Chiu

    IPC: H01L23/373 ,  H01L23/31 ,  H01L23/00 ,  H05K7/20 ,  H01L23/433

    Abstract: A power module including a circuit board, a chip, a first heat-conduction and insulation substrate and a second heat-conduction and insulation substrate is provided. The circuit board includes a board and a metal block embedded in the board and exposed from a first surface and a second surface of the board opposite to one another. The chip is disposed on a side of the second surface of the board corresponding to the metal block, and the chip is electrically and thermally connected to the metal block. The first heat-conduction and insulation substrate is located on a side of the first surface of the board to be disposed on the circuit board. The second heat-conduction and insulation substrate is electrically and thermally connected to the chip.

    CHIP PACKAGE
    7.
    发明申请
    CHIP PACKAGE 有权

    公开(公告)号：US20220310473A1

    公开(公告)日：2022-09-29

    申请号：US17839500

    申请日：2022-06-14

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/495 ,  H01L23/373 ,  H01L23/433

    Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

    Chip package
    8.
    发明授权
    Chip package 有权

    公开(公告)号：US11387159B2

    公开(公告)日：2022-07-12

    申请号：US16808369

    申请日：2020-03-04

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/31 ,  H01L23/433

    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

    CHIP PACKAGE
    9.
    发明申请
    CHIP PACKAGE 审中-公开

    公开(公告)号：US20190109064A1

    公开(公告)日：2019-04-11

    申请号：US15976886

    申请日：2018-05-11

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/495

    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

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