VEHICLE CONTROL DEVICE AND METHOD THEREOF

    公开(公告)号:US20230100219A1

    公开(公告)日:2023-03-30

    申请号:US17833935

    申请日:2022-06-07

    Abstract: A vehicle control device and a method thereof are provided. A master processor and a slave processor simultaneously receive, monitor or process signals of a vehicle, a power management module monitors the master processor via a first watchdog signal, and the master processor monitors the slave processor via a second watchdog signal. When the power management module sends the first watchdog signal to the master processor and no response message is received, the power management module sends a first reset signal to reset the master processor, and when the master processor sends the second watchdog signal to the slave processor and no response message is received, the master processor sends a second reset signal to reset the slave processor. When the master processor and the slave processor are abnormal, a forced wake-up module outputs a high level signal to forcibly wake up the master processor and the slave processor.

    Vehicle control device and method thereof

    公开(公告)号:US11989078B2

    公开(公告)日:2024-05-21

    申请号:US17833935

    申请日:2022-06-07

    Abstract: A vehicle control device and a method thereof are provided. A master processor and a slave processor simultaneously receive, monitor or process signals of a vehicle, a power management module monitors the master processor via a first watchdog signal, and the master processor monitors the slave processor via a second watchdog signal. When the power management module sends the first watchdog signal to the master processor and no response message is received, the power management module sends a first reset signal to reset the master processor, and when the master processor sends the second watchdog signal to the slave processor and no response message is received, the master processor sends a second reset signal to reset the slave processor. When the master processor and the slave processor are abnormal, a forced wake-up module outputs a high level signal to forcibly wake up the master processor and the slave processor.

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