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公开(公告)号：US12232433B2
公开(公告)日：2025-02-18
申请号：US17689604
申请日：2022-03-08
Applicant: Infineon Technologies AG
Inventor： Artur Wroblewski , Joel Hatsch , Christoph Saas , Stefan Seidl
Abstract: A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.
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公开(公告)号：US20250147565A1
公开(公告)日：2025-05-08
申请号：US18937565
申请日：2024-11-05
Applicant: Infineon Technologies AG
Inventor： Armin Krieg , Christoph Saas , Matthias Pichler
Abstract: In accordance with one embodiment, a consuming device is provided, comprising a power supply for an authentication chip of a consumable component, wherein the internal resistance of the power supply is variable, a detection device configured to capture information about an operating state of the authentication chip for a plurality of values of the internal resistance of the power supply and to determine a dependence of the operating state of the authentication chip on the internal resistance of the power supply, and an authentication circuit configured to authorize the use of the consumable component by the consuming device based on the determined dependence.
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公开(公告)号：US20220293852A1
公开(公告)日：2022-09-15
申请号：US17689604
申请日：2022-03-08
Applicant: Infineon Technologies AG
Inventor： Artur Wroblewski , Joel Hatsch , Christoph Saas , Stefan Seidl
Abstract: A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.
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公开(公告)号：US11496127B2
公开(公告)日：2022-11-08
申请号：US17523065
申请日：2021-11-10
Applicant: Infineon Technologies AG
Inventor： Manuel Schoeffmann , Christoph Saas
Abstract: Voltage monitoring circuit having an analog reset signal generator to generate a reset signal and coupled to a voltage to be monitored; first register to store a first state bit and coupled to the voltage to be monitored; second register connected in parallel to the first register, redundant to the first register, to store a second state bit, and coupled to the voltage to be monitored; logic coupled to the first and second registers and to determine a state control signal from the first and second state bits, and a second reset signal; and OR logic to receive the following signals on the input side and process them with one another according to an OR operation: a first reset signal generated by the analog reset signal generator and the second reset signal, so that a reset control signal is generated and fed to reset inputs of the registers.
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公开(公告)号：US10998276B2
公开(公告)日：2021-05-04
申请号：US16904132
申请日：2020-06-17
Applicant: Infineon Technologies AG
Inventor： Christoph Saas , Albert Missoni , Stefan Schneider , Dennis Tischendorf
Abstract: An integrated circuit having a node that is supplied by a first supply potential and is connected to a second supply potential in such a way that a leakage current flows between the node and the second supply potential, a detection circuit that is configured to detect a signal injected between the node and the second supply potential, the temporal variation of which is fast compared to a temporal variation of the leakage current, and a compensation circuit that is configured to compensate for a deviation in the potential of the node from the first supply potential with a delay which is large compared to the temporal variation of the signal.
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Patent Agency Ranking
公开(公告)号：US09768128B2
公开(公告)日：2017-09-19
申请号：US14166930
申请日：2014-01-29
Applicant: Infineon Technologies AG
Inventor： Thomas Kuenemund , Jan Otterstedt , Christoph Saas
CPC classification number: H01L23/57 , G01R31/2884 , G06F21/87 , G06F21/88 , H01L22/34 , H01L23/576 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
Abstract: According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal.
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7.发明申请公开(公告)号：US20250125283A1
公开(公告)日：2025-04-17
申请号：US18913488
申请日：2024-10-11
Applicant: Infineon Technologies AG
Inventor： Armin Krieg , Christoph Saas , Josef Haid
Abstract: A chip configured to be mounted on a carrier. The chip includes a die having an input/output circuit and a general-purpose input/output port, wherein the general-purpose input/output port is electrically conductively connected to the input/output circuit of the die. The chip further includes a package in which the die is at least partially embedded, and at least one metal surface on a mounting side of the chip, wherein the mounting side faces the carrier during mounting, wherein a size of the at least one metal surface is at least 10% of a size of the mounting side, and wherein the general-purpose input/output port is furthermore electrically conductively connected to the at least one metal surface.
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公开(公告)号：US20220147087A1
公开(公告)日：2022-05-12
申请号：US17522038
申请日：2021-11-09
Applicant: Infineon Technologies AG
Inventor： Christoph Mayerl , Albert Missoni , Christoph Saas
IPC: G05F1/575 , G05F1/571 , G01R19/165 , G05F3/26
Abstract: A voltage regulating circuit including a conversion circuit configured to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a predefined operating limiting voltage, and a regulator configured to receive the filtered analog voltage as regulation variable and to regulate an output voltage of the voltage regulating circuit to a predefined desired voltage.
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公开(公告)号：US11994891B2
公开(公告)日：2024-05-28
申请号：US17522038
申请日：2021-11-09
Applicant: Infineon Technologies AG
Inventor： Christoph Mayerl , Albert Missoni , Christoph Saas
IPC: G05F1/575 , G01R19/165 , G05F1/571 , G05F3/26
CPC classification number: G05F1/575 , G01R19/1659 , G05F1/571 , G05F3/262
Abstract: A voltage regulating circuit including a conversion circuit configured to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a predefined operating limiting voltage, and a regulator configured to receive the filtered analog voltage as regulation variable and to regulate an output voltage of the voltage regulating circuit to a predefined desired voltage.
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公开(公告)号：US20220149834A1
公开(公告)日：2022-05-12
申请号：US17523065
申请日：2021-11-10
Applicant: Infineon Technologies AG
Inventor： Manuel Schoeffmann , Christoph Saas
Abstract: Voltage monitoring circuit having an analog reset signal generator to generate a reset signal and coupled to a voltage to be monitored; first register to store a first state bit and coupled to the voltage to be monitored; second register connected in parallel to the first register, redundant to the first register, to store a second state bit, and coupled to the voltage to be monitored; logic coupled to the first and second registers and to determine a state control signal from the first and second state bits, and a second reset signal; and OR logic to receive the following signals on the input side and process them with one another according to an OR operation: a first reset signal generated by the analog reset signal generator and the second reset signal, so that a reset control signal is generated and fed to reset inputs of the registers.
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