公开(公告)号：US09485086B2

公开(公告)日：2016-11-01

申请号：US14872327

申请日：2015-10-01

Applicant: INPHI CORPORATION

Inventor： James L. Gorecki ,  Jiayun Zhang ,  Marcial K. Chua ,  Cosmin Iorga

IPC: H03H11/16 ,  H04L7/04 ,  H03L7/00 ,  H03K5/01 ,  H03K5/135 ,  H03K5/00

CPC classification number: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0807

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

公开(公告)号：US09548726B1

公开(公告)日：2017-01-17

申请号：US14622550

申请日：2015-02-13

Applicant: INPHI CORPORATION

Inventor： Cosmin Iorga ,  Jeffrey C. Yen

IPC: H03K3/012 ,  H03K17/56 ,  H03K17/16

CPC classification number: H03K17/56 ,  H03K17/165 ,  H03K19/00361 ,  H03K19/018585

Abstract: A driver integrated circuit (IC) device. The driver device can include a front-end module, a pre-driver module, and a driver module coupled to a transmission line path. The pre-driver module can be coupled to the front-end module and can include one or more delay adjust capacitor modules, and one or more pull-down control modules. The driver module can be coupled to the pre-driver module, the driver module including one or more pull-down control logic modules. This driver device can configured in several implementations to provide control and programmability of a driver slew rate to maximize a signal integrity eye opening.

Abstract translation: 驱动器集成电路（IC）装置。 驱动器设备可以包括前端模块，预驱动器模块和耦合到传输线路径的驱动器模块。 预驱动器模块可以耦合到前端模块，并且可以包括一个或多个延迟调整电容器模块以及一个或多个下拉控制模块。 驱动器模块可以耦合到预驱动器模块，驱动器模块包括一个或多个下拉控制逻辑模块。 该驱动器设备可以在几种实现中配置，以提供驱动器转换速率的控制和可编程性，以最大化信号完整性眼图打开。

公开(公告)号：US09160345B1

公开(公告)日：2015-10-13

申请号：US14477696

申请日：2014-09-04

Applicant: INPHI CORPORATION

Inventor： James L. Gorecki ,  Jiayun Zhang ,  Marcial K. Chua ,  Cosmin Iorga

IPC: H03H11/16 ,  H03L7/00 ,  H03K5/01 ,  H03K5/00

CPC classification number: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0807

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

Abstract translation: 公开了实现若干高性能相位内插器的装置。 一些实施例涉及一种全波积分相位插值核心，其包括以共源共轭结构布置的两对同相和正交相电流DAC，以驱动积分电容器并产生内插电压波形。 当前DAC被偏置，加权并由同相和正交相输入时钟控制，以产生呈现输入时钟的相位之间的相位值的内插波形。 部署内插器核心的一些实施例使用反馈电路和参考电压来调整内插电压波形的共模和幅度，以获得内插器线性区域或输出一致性范围内的最佳性能和操作。 单核和双核实现以及内插器内核的其他实现都表现出高电源抑制，高线性内插，宽频率范围和低成本占空比校正。

公开(公告)号：US09673972B2

公开(公告)日：2017-06-06

申请号：US15283735

申请日：2016-10-03

Applicant: INPHI CORPORATION

Inventor： James L. Gorecki ,  Jiayun Zhang ,  Marcial K. Chua ,  Cosmin Iorga

IPC: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03L7/00 ,  H03L7/06 ,  H03L7/08 ,  H03K5/00

CPC classification number: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0807

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.