公开(公告)号：US20130182489A1

公开(公告)日：2013-07-18

申请号：US13791807

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： David T. WANG

IPC: G11C29/04 ,  G11C11/24

CPC classification number: G11C29/04 ,  G11C11/24 ,  G11C11/40 ,  G11C29/76 ,  G11C29/808 ,  G11C29/846

Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.

公开(公告)号：US20150049539A1

公开(公告)日：2015-02-19

申请号：US14527644

申请日：2014-10-29

Applicant: INPHI CORPORATION

Inventor： David T. WANG

IPC: G11C29/04 ,  G11C11/24

CPC classification number: G11C29/04 ,  G11C11/24 ,  G11C11/40 ,  G11C29/76 ,  G11C29/808 ,  G11C29/846

Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.

Abstract translation: 提供存储器集成电路器件。 该设备包括多个常规地址输入和至少一个为所选模式或未选择模式配置的备用地址输入。 该装置包括多个控制输入，多个数据输入和多个数据输出。 该装置具有多个存储器阵列。 每个存储器阵列包括多个存储单元。 多个存储单元中的每一个耦合到数据输入/输出。 该设备具有包括多个备用存储器单元的存储器单元的备用组。 多个备用存储单元中的每一个都使用地址匹配表进行外部（或内部）可寻址，并配置有备用地址输入; 于是备用地址输入被耦合到地址匹配表以访问备用存储器单元。

公开(公告)号：US20150016192A1

公开(公告)日：2015-01-15

申请号：US14473872

申请日：2014-08-29

Applicant: INPHI CORPORATION

Inventor： Hamid Reza RATEGH ,  David T. WANG ,  Lawrence TSE

IPC: G11C29/04 ,  G11C11/413 ,  G11C16/08 ,  G11C7/10

CPC classification number: G11C29/04 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/06 ,  G11C11/413 ,  G11C16/08 ,  G11C29/08 ,  G11C29/44 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract translation: 集成电路器件。 该设备包括被配置为从地址流接收地址信息的地址输入，该地址信息来自耦合到主机控制器的地址命令总线和被配置为驱动地址信息的地址输出，并被耦合到多个存储器 DRAM）设备。 该设备具有包括非易失性存储器设备的地址匹配表，其被配置为至少存储对应于多个存储器（DRAM）设备中的至少一个的备用存储器位置和不良地址的修改地址。 该设备具有控制模块，该控制模块被配置为处理并确定每个地址是否与地址匹配表中存储的地址相匹配，以识别不良地址并将其配置为用备用存储器位置的修改地址替换坏地址。

公开(公告)号：US20140160874A1

公开(公告)日：2014-06-12

申请号：US14178241

申请日：2014-02-11

Applicant: INPHI CORPORATION

Inventor： David T. WANG

IPC: G11C11/4074

CPC classification number: G11C11/4074 ,  G11C5/148 ,  G11C11/4072 ,  G11C11/4093 ,  G11C2207/2227

Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.

Abstract translation: 一种用于操作存储器模块设备的方法。 该方法可以包括从主机存储器控制器传送芯片选择，命令和地址信息。 主机存储器控制器可以耦合到存储器接口设备，其可以耦合到存储器模块。 存储器模块可以包括多个存储器件。 可以使用命令和地址延迟（CAL）模式在存储器接口处接收芯片选择，命令和地址信息。 可以使用控制逻辑来启动从存储器接口设备中的输入终端电路的第一功率状态到第二功率状态的功率状态转换。

公开(公告)号：US20130176768A1

公开(公告)日：2013-07-11

申请号：US13782348

申请日：2013-03-01

Applicant: Inphi Corporation

Inventor： David T. WANG

IPC: G11C29/04 ,  G11C11/24

CPC classification number: G11C29/04 ,  G11C7/1012 ,  G11C11/24 ,  G11C11/408 ,  G11C11/4093 ,  G11C29/808 ,  G11C29/846

Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.