公开(公告)号：US10804913B1

公开(公告)日：2020-10-13

申请号：US16127103

申请日：2018-09-10

Applicant: INPHI CORPORATION

Inventor： Mrunmay Talegaonkar ,  Jorge Pernillo ,  Junyi Sun ,  Praveen Prabha ,  Chang-Feng Loi ,  Yu Liao ,  Jamal Riani ,  Belal Helal ,  Karthik Gopalakrishnan ,  Aaron Buchwald

IPC: H04L7/00 ,  H03L7/197 ,  H04L7/033 ,  H03L7/099 ,  H03L7/087 ,  H03L7/08

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.