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公开(公告)号：US20170257168A1
公开(公告)日：2017-09-07
申请号：US15061923
申请日：2016-03-04
Applicant: INPHI CORPORATION
Inventor： Karthik Gopalakrishnan , Jamal Riani , Arun Tiruvur
CPC classification number: H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US09548858B1
公开(公告)日：2017-01-17
申请号：US14997961
申请日：2016-01-18
Applicant: INPHI CORPORATION
Inventor： Halil Cirit , Karthik Gopalakrishnan , Pulkit Khandelwal , Ravindran Mohanavelu
CPC classification number: H04L7/0332 , H03L7/00 , H03L7/0807 , H04L5/0048 , H04L7/033 , H04L25/14 , H04L27/02 , H04Q2213/03
Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.
Abstract translation: 本发明涉及通信系统。 根据本发明的实施例，通信系统包括至少两个通信通道和偏斜管理模块。 偏斜管理模块基于两个通信通道的输出测试模式生成控制电流。 控制电流被积分，并通过比较器与参考电压进行比较，产生模拟偏移信号。 通信通道之一的PLL产生校正的时钟信号，其使用模拟偏移信号进行调整，以消除或调整通信通道之间的偏斜。 校正的时钟信号用于输出数据。 还有其它实施例。
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公开(公告)号：US10951318B2
公开(公告)日：2021-03-16
申请号：US16696913
申请日：2019-11-26
Applicant: INPHI CORPORATION
Inventor： Karthik Gopalakrishnan , Jamal Riani , Arun Tiruvur
IPC: H04B10/00 , H04L7/04 , H03K7/02 , H04B10/40 , H03K5/00 , H03K19/0185 , H03L7/093 , H03L7/099 , H03L7/197 , H03L7/23 , H04L7/00 , H04L25/00 , H04L25/49 , H04B10/54 , H04L7/033
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US20180131443A1
公开(公告)日：2018-05-10
申请号：US15809902
申请日：2017-11-10
Applicant: INPHI CORPORATION
Inventor： Karthik Gopalakrishnan , Jamal RIANI , Arun TIRUVUR
CPC classification number: H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US09866231B2
公开(公告)日：2018-01-09
申请号：US15426506
申请日：2017-02-07
Applicant: INPHI CORPORATION
Inventor： Michael Le , James Gorecki , Jamal Riani , Jorge Pernillo , Amber Tan , Karthik Gopalakrishnan , Belal Helal , Chang-Feng Loi , Irene Quek , Guojun Ren
CPC classification number: H03M1/38 , H03M1/0604 , H03M1/1038 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/468 , H04L25/03012 , H04L25/03019 , H04L25/03878
Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
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Patent Agency Ranking
公开(公告)号：US09602116B1
公开(公告)日：2017-03-21
申请号：US14990309
申请日：2016-01-07
Applicant: INPHI CORPORATION
Inventor： Michael Le , James Gorecki , Jamal Riani , Jorge Pernillo , Amber Tan , Karthik Gopalakrishnan , Belal Helal , Chang-Feng Loi , Irene Quek , Guojun Ren
CPC classification number: H03M1/38 , H03M1/0604 , H03M1/1038 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/468 , H04L25/03012 , H04L25/03019 , H04L25/03878
Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
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公开(公告)号：US10804913B1
公开(公告)日：2020-10-13
申请号：US16127103
申请日：2018-09-10
Applicant: INPHI CORPORATION
Inventor： Mrunmay Talegaonkar , Jorge Pernillo , Junyi Sun , Praveen Prabha , Chang-Feng Loi , Yu Liao , Jamal Riani , Belal Helal , Karthik Gopalakrishnan , Aaron Buchwald
Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
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公开(公告)号：US10148357B1
公开(公告)日：2018-12-04
申请号：US15604196
申请日：2017-05-24
Applicant: INPHI CORPORATION
Inventor： Halil Cirit , Karthik Gopalakrishnan , Karim Abdelhalim , Jorge Pernillo , Lawrence Tse
Abstract: Non-ideal downstream loading of a differential driver in a single ended circuit driving a communications laser—e.g., Electro absorption Modulated Laser (EML)—may be compensated by deploying a second matching network at the non-functional (terminated) driver output node. Certain embodiments may further compensate for distortion arising from circuit non-ideality, by introducing a laser replica downstream of the second matching network to mimic electrical properties of the laser. Embodiments may sufficiently compensate for downstream circuit non-ideality to allow replacing the bulky choke inductor of a bias tee, with a resistor. Substituting a resistor for a more complex inductor structure can simplify design and fabrication of the single-ended driver circuit, and also reduce footprint by eliminating area formerly occupied by the choke inductor. Embodiments may be particularly suited to bridge integration with other system components undergoing design migration toward double-ended modulator circuit architectures featuring a differential driver.
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公开(公告)号：US09847839B2
公开(公告)日：2017-12-19
申请号：US15061923
申请日：2016-03-04
Applicant: INPHI CORPORATION
Inventor： Karthik Gopalakrishnan , Jamal Riani , Arun Tiruvur
CPC classification number: H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US09825756B2
公开(公告)日：2017-11-21
申请号：US15375059
申请日：2016-12-09
Applicant: INPHI CORPORATION
Inventor： Halil Cirit , Karthik Gopalakrishnan , Pulkit Khandelwal , Ravindran Mohanavelu
CPC classification number: H04L7/0332 , H03L7/00 , H03L7/0807 , H04L5/0048 , H04L7/033 , H04L25/14 , H04L27/02 , H04Q2213/03
Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.
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