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公开(公告)号:US10804913B1
公开(公告)日:2020-10-13
申请号:US16127103
申请日:2018-09-10
Applicant: INPHI CORPORATION
Inventor: Mrunmay Talegaonkar , Jorge Pernillo , Junyi Sun , Praveen Prabha , Chang-Feng Loi , Yu Liao , Jamal Riani , Belal Helal , Karthik Gopalakrishnan , Aaron Buchwald
Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
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公开(公告)号:US09866231B2
公开(公告)日:2018-01-09
申请号:US15426506
申请日:2017-02-07
Applicant: INPHI CORPORATION
Inventor: Michael Le , James Gorecki , Jamal Riani , Jorge Pernillo , Amber Tan , Karthik Gopalakrishnan , Belal Helal , Chang-Feng Loi , Irene Quek , Guojun Ren
CPC classification number: H03M1/38 , H03M1/0604 , H03M1/1038 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/468 , H04L25/03012 , H04L25/03019 , H04L25/03878
Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
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公开(公告)号:US09602116B1
公开(公告)日:2017-03-21
申请号:US14990309
申请日:2016-01-07
Applicant: INPHI CORPORATION
Inventor: Michael Le , James Gorecki , Jamal Riani , Jorge Pernillo , Amber Tan , Karthik Gopalakrishnan , Belal Helal , Chang-Feng Loi , Irene Quek , Guojun Ren
CPC classification number: H03M1/38 , H03M1/0604 , H03M1/1038 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/468 , H04L25/03012 , H04L25/03019 , H04L25/03878
Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
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