公开(公告)号：US09722621B2

公开(公告)日：2017-08-01

申请号：US15375029

申请日：2016-12-09

Applicant: INPHI CORPORATION

Inventor： Mohammad Ranjbar ,  Jorge Pernillo

IPC: H03M1/10 ,  H03M1/68 ,  H03M1/38

CPC classification number: H03M1/1028 ,  H03K5/082 ,  H03M1/1023 ,  H03M1/36 ,  H03M1/38 ,  H03M1/662 ,  H03M1/68

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

公开(公告)号：US08884801B1

公开(公告)日：2014-11-11

申请号：US14086925

申请日：2013-11-21

Applicant: Inphi Corporation

Inventor： Mohammad Ranjbar

IPC: H03M1/12

CPC classification number: H03M1/0609 ,  H03M1/002 ,  H03M1/1215 ,  H03M1/145 ,  H03M1/365 ,  H03M1/466

Abstract: The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n−k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.

Abstract translation: 本发明涉及信号处理系统及其方法。 在各种实施例中，本发明提供一种模数转换（ADC）系统，其包括闪存ADC部分和时间交织的并行SAR部分。 对于n位ADC处理，闪速ADC部分在单个周期内转换n个位的k个MSB，并且SAR部分以m个周期数转换n-k个LSB。 SAR部分包括并行执行A / D转换的多个SAR信道，并且通过SAR部分验证来自过程闪存转换器的k个MSB的误差，并且通过减少精细数量来节省功耗的净节省 分辨率SAR。 还有其它实施例。

公开(公告)号：US09548754B1

公开(公告)日：2017-01-17

申请号：US15146214

申请日：2016-05-04

Applicant: INPHI CORPORATION

Inventor： Mohammad Ranjbar ,  Jorge Pernillo

IPC: H03M1/10 ,  H03M1/68 ,  H03M1/38

CPC classification number: H03M1/1028 ,  H03K5/082 ,  H03M1/1023 ,  H03M1/36 ,  H03M1/38 ,  H03M1/662 ,  H03M1/68

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Abstract translation: 本发明涉及集成电路及其方法。 更具体地，本发明的实施例提供了一种比较器校准环路，其中数字积分器基于比较器的输出存储运行总和。 DAC转换运行总和并产生偏移校准电压，该电压由低通滤波器模块滤波，滤波后的偏移校准电压用于消除比较器的固有失调电压和低频噪声。 还有其它实施例。

公开(公告)号：US09356615B1

公开(公告)日：2016-05-31

申请号：US14935306

申请日：2015-11-06

Applicant: INPHI CORPORATION

Inventor： Mohammad Ranjbar ,  Jorge Pernillo

IPC: H03M1/10 ,  H03M1/68 ,  H03M1/38

CPC classification number: H03M1/1028 ,  H03K5/082 ,  H03M1/1023 ,  H03M1/36 ,  H03M1/38 ,  H03M1/662 ,  H03M1/68

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Abstract translation: 本发明涉及集成电路及其方法。 更具体地，本发明的实施例提供了一种比较器校准环路，其中数字积分器基于比较器的输出存储运行总和。 DAC转换运行总和并产生偏移校准电压，该电压由低通滤波器模块滤波，滤波后的偏移校准电压用于消除比较器的固有失调电压和低频噪声。 还有其它实施例。

公开(公告)号：US09331706B1

公开(公告)日：2016-05-03

申请号：US14511074

申请日：2014-10-09

Applicant: INPHI CORPORATION

Inventor： Mohammad Ranjbar

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0609 ,  H03M1/002 ,  H03M1/1215 ,  H03M1/145 ,  H03M1/365 ,  H03M1/466

Abstract: The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n−k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.

Abstract translation: 本发明涉及信号处理系统及其方法。 在各种实施例中，本发明提供一种模数转换（ADC）系统，其包括闪存ADC部分和时间交织的并行SAR部分。 对于n位ADC处理，闪速ADC部分在单个周期内转换n个位的k个MSB，并且SAR部分以m个周期数转换n-k个LSB。 SAR部分包括并行执行A / D转换的多个SAR信道，并且通过SAR部分验证来自过程闪存转换器的k个MSB的误差，并且通过减少精细数量来节省功耗的净节省 分辨率SAR。 还有其它实施例。