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Patent Agency Ranking
公开(公告)号：US20240007072A1
公开(公告)日：2024-01-04
申请号：US18038371
申请日：2021-07-27
Inventor： Yingqiang YAN , Chuan HU , Xun XIANG , Wei ZHENG , Zhitao CHEN , Zhikuan CHEN
IPC: H03H1/00
CPC classification number: H03H1/0007 , H03H2001/0021
Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.
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公开(公告)号：US20240153913A1
公开(公告)日：2024-05-09
申请号：US18417789
申请日：2024-01-19
Inventor： Yinhua CUI , Wei ZHENG , Yao WANG , Zhikuan CHEN , Chuan HU , Zhitao CHEN , Chang'an WANG
IPC: H01L25/065 , H01L21/02 , H01L21/768 , H01L23/00
CPC classification number: H01L25/0652 , H01L21/02115 , H01L21/76898 , H01L24/13 , H01L24/29 , H01L2224/13009 , H01L2224/13025 , H01L2224/29005 , H01L2224/29023 , H01L2924/10253 , H01L2924/1306 , H01L2924/182
Abstract: A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.
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公开(公告)号：US20240283132A1
公开(公告)日：2024-08-22
申请号：US18624251
申请日：2024-04-02
Inventor： Yingqiang YAN , Chuan HU , Wei ZHENG , Yunshi LING , Zhikuan CHEN , Zhitao CHEN
IPC: H01Q1/22 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/065
CPC classification number: H01Q1/2283 , H01L21/568 , H01L23/3121 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L2224/24137 , H01L2224/821
Abstract: A fan-out package structure and a fabricating method therefor are provided. The structure includes an encapsulation layer; an antenna RF module assembly and electronic component(s) embedded in the encapsulation layer; a first rewiring layer on a surface of a first side of the encapsulation layer, electrically connected to at least part of the pins of the assembly and to at least part of the pins of the electronic component(s); a second rewiring layer on a surface of a second side of the encapsulation layer, electrically connected to the encapsulation layer-interconnection conductive pillars and to the conductive solder balls/bumps; and conductive solder balls/bumps on a side of the second rewiring layer away from the encapsulation layer. The assembly includes a RF substrate, and an antenna array and RF device(s) arranged thereon. The assembly is embedded in the first side. Encapsulation-layer interconnection conductive pillars are formed in the encapsulation layer.
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4.发明公开公开(公告)号：US20240136297A1
公开(公告)日：2024-04-25
申请号：US18112590
申请日：2023-02-22
Inventor： Yingqiang YAN , Chuan HU , Yao WANG , Wei ZHENG , Zhitao CHEN
IPC: H01L23/538 , H01L21/56 , H01L23/00 , H01L25/065
CPC classification number: H01L23/5389 , H01L21/561 , H01L21/568 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L2224/24137 , H01L2224/24141 , H01L2224/32245 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/95001 , H01L2224/96
Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.
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5.发明公开公开(公告)号：US20240234328A9
公开(公告)日：2024-07-11
申请号：US18112590
申请日：2023-02-22
Inventor： Yingqiang YAN , Chuan HU , Yao WANG , Wei ZHENG , Zhitao CHEN
IPC: H01L23/538 , H01L21/56 , H01L23/00 , H01L25/065
CPC classification number: H01L23/5389 , H01L21/561 , H01L21/568 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L2224/24137 , H01L2224/24141 , H01L2224/32245 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/95001 , H01L2224/96
Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.
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