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公开(公告)号：US12112956B2
公开(公告)日：2024-10-08
申请号：US17434480
申请日：2021-02-08
Inventor： Yao Wang , Zibai Li , Yunzhi Ling , Xun Xiang , Yinhua Cui , Chuan Hu , Zhitao Chen
IPC: H01L21/48 , H01L23/538 , H01L25/065 , H01L23/00
CPC classification number: H01L21/485 , H01L21/4857 , H01L21/486 , H01L23/5383 , H01L25/0655 , H01L24/19 , H01L24/20 , H01L2224/211 , H01L2924/381
Abstract: Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the chip corresponding in projection position.
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公开(公告)号：US20240186254A1
公开(公告)日：2024-06-06
申请号：US18162110
申请日：2023-01-31
Inventor： Yunzhi LING , Yingqiang YAN , Xun XIANG , Chuan HU , Wei ZHAO , Zhitao CHEN
IPC: H01L23/538 , H01L21/48 , H01L23/31 , H01L23/498
CPC classification number: H01L23/5383 , H01L21/4857 , H01L23/3185 , H01L23/49816
Abstract: Disclosed are a method for manufacturing a carrier structure suitable for chiplet fine lines and a carrier structure. The method includes: preparing a temporary bonding layer on a temporary carrier, and preparing a pin interconnection layer on the temporary bonding layer, preparing at least one fine line interconnection layer on the pin interconnection layer; preparing a core layer on the at least one fine line interconnection layer with a second electrically conductive structure interconnected with the at least one fine line interconnection layer and/or the pin interconnection layer, preparing at least one build-up layer connected to the fine line interconnection layer on the core layer, and de-bonding the temporary bonding layer to obtain the carrier structure. The solutions can prepare fine lines on a carrier structure and ensure the yield of fine line interconnection lines, thus improving the manufacturability of the fine lines, carrier structure and packaging structure.
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公开(公告)号：US20240153913A1
公开(公告)日：2024-05-09
申请号：US18417789
申请日：2024-01-19
Inventor： Yinhua CUI , Wei ZHENG , Yao WANG , Zhikuan CHEN , Chuan HU , Zhitao CHEN , Chang'an WANG
IPC: H01L25/065 , H01L21/02 , H01L21/768 , H01L23/00
CPC classification number: H01L25/0652 , H01L21/02115 , H01L21/76898 , H01L24/13 , H01L24/29 , H01L2224/13009 , H01L2224/13025 , H01L2224/29005 , H01L2224/29023 , H01L2924/10253 , H01L2924/1306 , H01L2924/182
Abstract: A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.
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公开(公告)号：US20220149007A1
公开(公告)日：2022-05-12
申请号：US17047731
申请日：2020-06-16
Inventor： Yuan BAO , Xun XIANG , Yao WANG , Yingqiang YAN , Chuan HU , Zhitao CHEN
IPC: H01L25/065 , H01L21/56 , H01L25/00
Abstract: The present disclosure provides a chip packaging structure and method, using a back-to-back packaging structure, and realizing electrical connection between chips through TSV holes or cooperation between TSV and TMV holes, completely penetrating two chips. Thus, the TSV hole passing through a silicon material may not need to be formed in advance on the chips before bonding the chips, thereby the requirement of alignment accuracy of the chips can be reduced, and the process difficulty can be reduced. In addition, as the back-to-back packaging process is adopted, the heat dissipation efficiency of the chips can be improved, and the problem of circuit breakage due to materials with different expansion coefficients present between the chips can be avoided.
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5.发明公开公开(公告)号：US20240234328A9
公开(公告)日：2024-07-11
申请号：US18112590
申请日：2023-02-22
Inventor： Yingqiang YAN , Chuan HU , Yao WANG , Wei ZHENG , Zhitao CHEN
IPC: H01L23/538 , H01L21/56 , H01L23/00 , H01L25/065
CPC classification number: H01L23/5389 , H01L21/561 , H01L21/568 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L2224/24137 , H01L2224/24141 , H01L2224/32245 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/95001 , H01L2224/96
Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.
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Patent Agency Ranking
公开(公告)号：US20240038705A1
公开(公告)日：2024-02-01
申请号：US17918038
申请日：2022-07-28
Inventor： Yunzhi LING , Siliang HE , Jianguo MA , Yuhao BI , Xingyu LIU , Chuan HU , Zhitao CHEN
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/73 , H01L24/92 , H01R4/58 , H01R43/00 , H01L2224/0345 , H01L2224/05573 , H01L2224/1146 , H01L2224/13016 , H01L2224/13082 , H01L2224/13147 , H01L2224/13111 , H01L2224/13109 , H01L2224/16057 , H01L2224/2919 , H01L2924/0665 , H01L2224/321 , H01L2224/73204 , H01L2224/81201 , H01L2224/81898 , H01L2224/81948 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2224/83102 , H01L2224/83855 , H01L2224/9205
Abstract: A substrate bonding method includes: providing a first and a second substrate; forming, on the first substrate, a first metal micro-bump array including first metal pillar(s) formed on the first substrate and first metal nanowires formed thereon and spaced apart from each other; forming, on the second substrate, a second metal micro-bump array including second metal pillar(s) formed on the second substrate and second metal nanowires formed thereon and spaced apart from each other; pressing the first substrate onto the second substrate, such that the first and second metal micro-bump arrays are positioned and staggered with each other, forming a physically interwoven interlocking structure between the first and second metal nanowires; applying a filling material between the first and second substrates; curing the filling material to form a bonding cavity; and then performing confined heating reflux on the first and second metal micro-bump arrays in the bonding cavity.
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公开(公告)号：US20230245944A1
公开(公告)日：2023-08-03
申请号：US17635437
申请日：2021-07-28
Inventor： Yingqiang Yan , Chuan Hu , Zhikuan Chen , Zhitao Chen
IPC: H01L23/367 , H01L23/29 , H01L21/56
CPC classification number: H01L23/3675 , H01L23/29 , H01L21/56
Abstract: A fan-out type package and a preparation method of the fan-out type package are provided. The fan-out type package has one or more chips having same or different functions and each having a back surface mounted in a chip mounting region of the heat dissipation sheet via the adhesive material layer, and a front surface covered by a temporary protection material; an adhesive material layer; a heat dissipation sheet; an encapsulation material layer formed by making an encapsulation material flow into and fill a gap between the temporary protection material and the heat dissipation sheet and/or cover a side of the heat dissipation sheet opposite to a side thereof mounted with the chip, and then removing the temporary protection material; a packaging circuit grown on the front surface of the chip, the encapsulation material, and the heat dissipation sheet; and a packaging circuit protection layer protecting the packaging circuit.
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公开(公告)号：US12184253B2
公开(公告)日：2024-12-31
申请号：US18038371
申请日：2021-07-27
Inventor： Yingqiang Yan , Chuan Hu , Xun Xiang , Wei Zheng , Zhitao Chen , Zhikuan Chen
IPC: H03H1/00
Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.
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公开(公告)号：US20240304556A1
公开(公告)日：2024-09-12
申请号：US18503950
申请日：2023-11-07
Inventor： Xun XIANG , Chuan HU , Yingqiang YAN , Yunzhi LING , Zhikuan CHEN , Zhitao CHEN
IPC: H01L23/538 , H01L21/56 , H01L23/00 , H01L23/498 , H01L25/065
CPC classification number: H01L23/5381 , H01L21/563 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/29 , H01L25/0655 , H01L2224/05005 , H01L2224/05025 , H01L2224/29009 , H01L2224/29026 , H01L2924/10253 , H01L2924/18161 , H01L2924/18162
Abstract: Disclosed is a method of manufacturing a chiplet-fine-interconnection-package structure, comprising: mounting at least two chips on a first side surface of a substrate and preparing a temporary bonding layer on the chips, preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer; releasing the temporary bonding layer, and bonding a silicon bridge structure on the first pin-arrays of the two adjacent chips. The solution provided by the present invention makes it unnecessary to remove the substrate in the subsequent process and to perform grinding and thinning process on the corresponding position of the plastic package layer, thus simplifying the packaging process steps and reducing the packaging cost.
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公开(公告)号：US20240283132A1
公开(公告)日：2024-08-22
申请号：US18624251
申请日：2024-04-02
Inventor： Yingqiang YAN , Chuan HU , Wei ZHENG , Yunshi LING , Zhikuan CHEN , Zhitao CHEN
IPC: H01Q1/22 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/065
CPC classification number: H01Q1/2283 , H01L21/568 , H01L23/3121 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L2224/24137 , H01L2224/821
Abstract: A fan-out package structure and a fabricating method therefor are provided. The structure includes an encapsulation layer; an antenna RF module assembly and electronic component(s) embedded in the encapsulation layer; a first rewiring layer on a surface of a first side of the encapsulation layer, electrically connected to at least part of the pins of the assembly and to at least part of the pins of the electronic component(s); a second rewiring layer on a surface of a second side of the encapsulation layer, electrically connected to the encapsulation layer-interconnection conductive pillars and to the conductive solder balls/bumps; and conductive solder balls/bumps on a side of the second rewiring layer away from the encapsulation layer. The assembly includes a RF substrate, and an antenna array and RF device(s) arranged thereon. The assembly is embedded in the first side. Encapsulation-layer interconnection conductive pillars are formed in the encapsulation layer.
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