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公开(公告)号：US20240153913A1
公开(公告)日：2024-05-09
申请号：US18417789
申请日：2024-01-19
发明人： Yinhua CUI , Wei ZHENG , Yao WANG , Zhikuan CHEN , Chuan HU , Zhitao CHEN , Chang'an WANG
IPC分类号： H01L25/065 , H01L21/02 , H01L21/768 , H01L23/00
CPC分类号： H01L25/0652 , H01L21/02115 , H01L21/76898 , H01L24/13 , H01L24/29 , H01L2224/13009 , H01L2224/13025 , H01L2224/29005 , H01L2224/29023 , H01L2924/10253 , H01L2924/1306 , H01L2924/182
摘要： A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.
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公开(公告)号：US20240007072A1
公开(公告)日：2024-01-04
申请号：US18038371
申请日：2021-07-27
发明人： Yingqiang YAN , Chuan HU , Xun XIANG , Wei ZHENG , Zhitao CHEN , Zhikuan CHEN
IPC分类号： H03H1/00
CPC分类号： H03H1/0007 , H03H2001/0021
摘要： A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.
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公开(公告)号：US20240304556A1
公开(公告)日：2024-09-12
申请号：US18503950
申请日：2023-11-07
发明人： Xun XIANG , Chuan HU , Yingqiang YAN , Yunzhi LING , Zhikuan CHEN , Zhitao CHEN
IPC分类号： H01L23/538 , H01L21/56 , H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L23/5381 , H01L21/563 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/29 , H01L25/0655 , H01L2224/05005 , H01L2224/05025 , H01L2224/29009 , H01L2224/29026 , H01L2924/10253 , H01L2924/18161 , H01L2924/18162
摘要： Disclosed is a method of manufacturing a chiplet-fine-interconnection-package structure, comprising: mounting at least two chips on a first side surface of a substrate and preparing a temporary bonding layer on the chips, preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer; releasing the temporary bonding layer, and bonding a silicon bridge structure on the first pin-arrays of the two adjacent chips. The solution provided by the present invention makes it unnecessary to remove the substrate in the subsequent process and to perform grinding and thinning process on the corresponding position of the plastic package layer, thus simplifying the packaging process steps and reducing the packaging cost.
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公开(公告)号：US20240283132A1
公开(公告)日：2024-08-22
申请号：US18624251
申请日：2024-04-02
发明人： Yingqiang YAN , Chuan HU , Wei ZHENG , Yunshi LING , Zhikuan CHEN , Zhitao CHEN
IPC分类号： H01Q1/22 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/065
CPC分类号： H01Q1/2283 , H01L21/568 , H01L23/3121 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L2224/24137 , H01L2224/821
摘要： A fan-out package structure and a fabricating method therefor are provided. The structure includes an encapsulation layer; an antenna RF module assembly and electronic component(s) embedded in the encapsulation layer; a first rewiring layer on a surface of a first side of the encapsulation layer, electrically connected to at least part of the pins of the assembly and to at least part of the pins of the electronic component(s); a second rewiring layer on a surface of a second side of the encapsulation layer, electrically connected to the encapsulation layer-interconnection conductive pillars and to the conductive solder balls/bumps; and conductive solder balls/bumps on a side of the second rewiring layer away from the encapsulation layer. The assembly includes a RF substrate, and an antenna array and RF device(s) arranged thereon. The assembly is embedded in the first side. Encapsulation-layer interconnection conductive pillars are formed in the encapsulation layer.
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