公开(公告)号：US10777275B2

公开(公告)日：2020-09-15

申请号：US16143033

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Agostino Pirovano ,  Hernan A. Castro ,  Innocenzo Tortorelli ,  Andrea Redaelli

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.

公开(公告)号：US11647638B2

公开(公告)日：2023-05-09

申请号：US16295687

申请日：2019-03-07

Applicant: INTEL CORPORATION

Inventor： Anna Maria Conti ,  Fabio Pellizzer ,  Agostino Pirovano ,  Kolya Yastrebenetsky

IPC: H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

公开(公告)号：US10163982B2

公开(公告)日：2018-12-25

申请号：US15474154

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Fabio Pellizzer ,  Agostino Pirovano ,  DerChang Kau

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  G11C13/00

Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.