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公开(公告)号：US20180095929A1
公开(公告)日：2018-04-05
申请号：US15281376
申请日：2016-09-30
Applicant: INTEL CORPORATION
Inventor： Zoran Zivkovic , Aleksandar Beric
IPC: G06F15/173 , G11C7/22 , G11C7/10 , G06F3/06 , G06F13/42
CPC classification number: G06F15/17318 , G06F13/4234 , G06F13/4286 , G06F15/8061 , G11C8/12
Abstract: An apparatus for localized and random data access is described herein. The apparatus includes a multi-bank memory, a queue, and an output buffer. The multi-bank memory is to store addresses locations of imaging data. The queue corresponds to each bank of the multi-bank memory, and the queue is to store addresses from the multi-bank memory for data access. The output buffer is to store data accessed based on addresses from the queue.
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2.发明授权公开(公告)号：US10572982B2
公开(公告)日：2020-02-25
申请号：US15724993
申请日：2017-10-04
Applicant: Intel Corporation
Inventor： Aleksandar Beric , Kari Pulli , Nemanja Jankovic , Zoran Zivkovic
Abstract: Techniques related to image distortion correction for images captured by using a wide-angle lens include homography and a lens distortion correction using a radial-ratio-based look up table.
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公开(公告)号：US09407926B2
公开(公告)日：2016-08-02
申请号：US14287967
申请日：2014-05-27
Applicant: Intel Corporation
Inventor： Vladimir Kovacevic , Zdravko Pantic , Aleksandar Beric , Ramanathan Sethuraman , Jean-Pierre Giacalone , Anton Igorevich Veselov , Marat Ravilevich Gilmutdinov
IPC: G06K9/34 , H04N19/503 , G06T7/20 , H04N19/176 , H04N19/102 , H04N19/14 , H04N19/137 , H04N19/85 , H04N19/587
CPC classification number: H04N19/503 , H04N19/102 , H04N19/137 , H04N19/14 , H04N19/176 , H04N19/587 , H04N19/85
Abstract: Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example methods can also include processing the first plurality of pixel blocks and a second plurality of pixel blocks corresponding to a prior second frame of the video sequence to create, based on a first criterion, a map identifying one or more static pixel blocks in the first plurality of pixel blocks. Such example methods can further include identifying, based on the map, a static region in the first frame of the video sequence.
Abstract translation: 公开了用于执行视频处理的基于块的静态区域检测的方法，装置，系统和制品。 公开的示例视频处理方法包括将视频序列的第一帧中的像素分割为第一多个像素块。 这样的示例性方法还可以包括处理第一多个像素块和与视频序列的先前第二帧相对应的第二多个像素块，以基于第一准则创建标识一个或多个静态像素块中的一个或多个静态像素块的映射 第一多个像素块。 这样的示例方法还可以包括基于该图来识别视频序列的第一帧中的静态区域。
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公开(公告)号：US09275468B2
公开(公告)日：2016-03-01
申请号：US14252944
申请日：2014-04-15
Applicant: Intel Corporation
Inventor： Vladimir Kovacevic , Zdravko Pantic , Aleksandar Beric , Milos Markovic , Vladimir Ilic
CPC classification number: G06T7/20 , G06K9/46 , G06K9/52 , G06K9/6215 , G06K2009/4666 , G06T7/262 , G06T2207/10016 , G06T2207/20021 , G06T2207/20056
Abstract: Techniques related to managing the use of motion estimation in video processing are discussed. Such techniques may include determining dividing two video frames each into corresponding regions, generating phase plane correlations for the corresponding regions, determining whether the video frames are motion estimation correlated based on the phase plane correlations, and providing a video frame prediction mode indicator based on the determination.
Abstract translation: 讨论了与视频处理中运动估计的使用有关的技术。 这样的技术可以包括确定将两个视频帧分成对应的区域，产生相应区域的相位平面相关性，基于相位平面相关性确定视频帧是否是运动估计相关的，以及基于 决心。
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公开(公告)号：US20150379666A1
公开(公告)日：2015-12-31
申请号：US14317234
申请日：2014-06-27
Applicant: Intel Corporation
Inventor： Dmitar Redzic , Aleksandar Beric , Edwin Van Dalen
CPC classification number: G06T1/20 , G06T3/0093 , G06T3/4007 , G06T2200/28
Abstract: Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.
Abstract translation: 提出了允许有效的基于像素的图像和/或视频翘曲和缩放的技术。 图像处理系统可以包括与存储器通信地耦合的存储器和加速器单元。 加速器单元可以基于配置设置从存储器接收输入图像的至少一部分作为相邻四角形状的阵列; 并且通过以下方式处理每个形状：通过线性化来确定由形状的四个角位置描绘的输出像素的阵列的位置; 内插输出像素阵列的每个像素的值; 以及将内插的像素值存储在存储器中。 对于翘曲，相邻的四角形状的阵列可以包括近似失真的四边形的阵列，其近似输入图像的失真，并且内插的像素值可以表示翘曲的输出图像。 对于缩放，相邻四角形状的阵列可以包括相邻矩形的阵列。
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Patent Agency Ranking
公开(公告)号：US20180095877A1
公开(公告)日：2018-04-05
申请号：US15281288
申请日：2016-09-30
Applicant: INTEL CORPORATION
Inventor： Aleksandar Beric , Zoran Zivkovic
IPC: G06F12/0802 , G06K9/00
CPC classification number: G06F12/0802 , G06F2212/301 , G06K9/00 , G06K9/00221 , G06K9/00986
Abstract: An example apparatus for processing scattered data includes an address buffer to receive a plurality of vector addresses corresponding to input vector data comprising scattered samples to be processed. The apparatus also includes a multi-bank memory to receive the input vector data and send output vector data. The apparatus further includes a memory controller comprising an address scheduler to assign an address to each bank of the multi-bank memory.
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公开(公告)号：US20140149657A1
公开(公告)日：2014-05-29
申请号：US14129178
申请日：2012-12-28
Applicant: INTEL CORPORATION
Inventor： Radomir Jakovljevic , Aleksandar Beric , Edwin Van Dalen , Dragan Milicev
CPC classification number: G06F5/08 , G06F9/3004 , G06F9/30043 , G06F9/3887 , G06F12/0207 , G06F12/04 , G06F15/8007
Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.
Abstract translation: 可以提供一种电子设备，其包括用于执行操作的处理器，以及包括多个并行存储器组的存储器子系统，以使用偏移方案来存储数据的二维（2D）数组。 每个存储体可以包括每个字库的至少两个元素。
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公开(公告)号：US10001971B2
公开(公告)日：2018-06-19
申请号：US15076118
申请日：2016-03-21
Applicant: INTEL CORPORATION
Inventor： Radomir Jakovljevic , Aleksandar Beric , Edwin Van Dalen , Dragan Milicev
CPC classification number: G06F5/08 , G06F9/3004 , G06F9/30043 , G06F9/3887 , G06F12/0207 , G06F12/04 , G06F15/8007
Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.
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公开(公告)号：US09443281B2
公开(公告)日：2016-09-13
申请号：US14317234
申请日：2014-06-27
Applicant: Intel Corporation
Inventor： Dmitar Redzic , Aleksandar Beric , Edwin Van Dalen
CPC classification number: G06T1/20 , G06T3/0093 , G06T3/4007 , G06T2200/28
Abstract: Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.
Abstract translation: 提出了允许有效的基于像素的图像和/或视频翘曲和缩放的技术。 图像处理系统可以包括与存储器通信地耦合的存储器和加速器单元。 加速器单元可以基于配置设置从存储器接收输入图像的至少一部分作为相邻四角形状的阵列; 并且通过以下方式处理每个形状：通过线性化来确定由形状的四个角位置描绘的输出像素的阵列的位置; 内插输出像素阵列的每个像素的值; 以及将内插的像素值存储在存储器中。 对于翘曲，相邻的四角形状的阵列可以包括近似失真的四边形的阵列，其近似输入图像的失真，并且内插的像素值可以表示翘曲的输出图像。 对于缩放，相邻四角形状的阵列可以包括相邻矩形的阵列。
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公开(公告)号：US09329834B2
公开(公告)日：2016-05-03
申请号：US14129178
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Radomir Jakovljevic , Aleksandar Beric , Edwin Van Dalen , Dragan Milicev
CPC classification number: G06F5/08 , G06F9/3004 , G06F9/30043 , G06F9/3887 , G06F12/0207 , G06F12/04 , G06F15/8007
Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.
Abstract translation: 可以提供一种电子设备，其包括用于执行操作的处理器，以及包括多个并行存储器组的存储器子系统，以使用偏移方案来存储数据的二维（2D）数组。 每个存储体可以包括每个字库的至少两个元素。
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