公开(公告)号：US20190107879A1

公开(公告)日：2019-04-11

申请号：US16158190

申请日：2018-10-11

Applicant: INTEL CORPORATION

Inventor： Paul S. DIEFENBAUGH ,  Eugene GORBATOV ,  Andrew HENROID ,  Eric C. SAMSON ,  Barnes COOPER

IPC: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

公开(公告)号：US20170097670A1

公开(公告)日：2017-04-06

申请号：US15263274

申请日：2016-09-12

Applicant: INTEL CORPORATION

Inventor： Paul S. DIEFENBAUGH ,  Eugene GORBATOV ,  Andrew HENROID ,  Eric C. SAMSON ,  Barnes COOPER

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.