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Patent Agency Ranking
公开(公告)号：US20150185808A1
公开(公告)日：2015-07-02
申请号：US14142791
申请日：2013-12-28
Applicant: INTEL CORPORATION
Inventor： Robert E. GOUGH , Mazen G. GEDEON , Barnes COOPER , Basavaraj B. ASTEKAR , Sean C. DARDIS
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3231 , G06F1/3253 , G06F1/3293 , Y02D10/122 , Y02D10/151 , Y02D10/173 , Y02D50/20
Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.
Abstract translation: 可以提供一种电子设备，其包括第一控制器，第二控制器和总线以在第一控制器和第二控制器之间连接。 电子设备还可以包括在第一控制器和第二控制器之间的第一信号线，以及第一控制器，以在第一信号线上向第二控制器提供第一信号，以将第二控制器从低功率模式唤醒。
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公开(公告)号：US20180098191A1
公开(公告)日：2018-04-05
申请号：US15283348
申请日：2016-10-01
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Barnes COOPER , Tawfik M. RAHAL-ARABI
Abstract: Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.
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公开(公告)号：US20180046240A1
公开(公告)日：2018-02-15
申请号：US15634805
申请日：2017-06-27
Applicant: INTEL CORPORATION
Inventor： Robert E. GOUGH , Mazen G. GEDEON , Barnes COOPER , Basavaraj B. ASTEKAR , Sean C. DARDIS
IPC: G06F1/32
Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.
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公开(公告)号：US20190107879A1
公开(公告)日：2019-04-11
申请号：US16158190
申请日：2018-10-11
Applicant: INTEL CORPORATION
Inventor： Paul S. DIEFENBAUGH , Eugene GORBATOV , Andrew HENROID , Eric C. SAMSON , Barnes COOPER
IPC: G06F1/3234 , G06F1/3246 , G06F1/3287
CPC classification number: G06F1/3234 , G06F1/3246 , G06F1/3287 , G06F9/4893 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
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公开(公告)号：US20170097670A1
公开(公告)日：2017-04-06
申请号：US15263274
申请日：2016-09-12
Applicant: INTEL CORPORATION
Inventor： Paul S. DIEFENBAUGH , Eugene GORBATOV , Andrew HENROID , Eric C. SAMSON , Barnes COOPER
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3246 , G06F1/3287 , G06F9/4893 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
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