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    APPARATUS AND METHOD FOR DYNAMIC CONTROL OF MICROPROCESSOR CONFIGURATION
    1.
    发明申请
    APPARATUS AND METHOD FOR DYNAMIC CONTROL OF MICROPROCESSOR CONFIGURATION 有权

    公开(公告)号：US20210303357A1

    公开(公告)日：2021-09-30

    申请号：US16833595

    申请日：2020-03-28

    Applicant: Intel Corporation

    Inventor： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

    IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

    ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS
    2.
    发明申请
    ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS 审中-公开

    公开(公告)号：US20190086974A1

    公开(公告)日：2019-03-21

    申请号：US16192632

    申请日：2018-11-15

    Applicant: Intel Corporation

    Inventor： Muhammad ABOZAED ,  Eugene GORBATOV ,  Gaurav KHANNA ,  Avinash N. ANANTHAKRISHNAN

    IPC: G06F1/20 ,  G06F9/48 ,  G06F1/32

    Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

    PEAK POWER DETERMINATION FOR AN INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    PEAK POWER DETERMINATION FOR AN INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20200264692A1

    公开(公告)日：2020-08-20

    申请号：US16642694

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Eugene GORBATOV ,  Alexander UAN-ZO-LI ,  Chee Lim NGE ,  James HERMERDING, II ,  Zhongsheng WANG

    IPC: G06F1/3296 ,  G06F1/28

    Abstract: Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

    ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS
    4.
    发明申请
    ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS 审中-公开

    公开(公告)号：US20200218320A1

    公开(公告)日：2020-07-09

    申请号：US16707932

    申请日：2019-12-09

    Applicant: Intel Corporation

    Inventor： Muhammad ABOZAED ,  Eugene GORBATOV ,  Gaurav KHANNA ,  Avinash N. ANANTHAKRISHNAN

    IPC: G06F1/20 ,  G06F9/48 ,  G06F1/3206

    Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

    TECHNIQUES TO COMPOSE MEMORY RESOURCES ACROSS DEVICES
    5.
    发明申请
    TECHNIQUES TO COMPOSE MEMORY RESOURCES ACROSS DEVICES 审中-公开

    公开(公告)号：US20180267826A1

    公开(公告)日：2018-09-20

    申请号：US15790444

    申请日：2017-10-23

    Applicant: INTEL CORPORATION

    Inventor： Neven M. ABOU GAZALA ,  Paul S. DIEFENBAUGH ,  Nithyananda S. JEGANATHAN ,  Eugene GORBATOV

    IPC: G06F9/46 ,  G06F12/0868

    Abstract: Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.

    ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS
    8.
    发明申请
    ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS 审中-公开

    公开(公告)号：US20180095509A1

    公开(公告)日：2018-04-05

    申请号：US15283349

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Muhammad ABOZAED ,  Eugene GORBATOV ,  Gaurav KHANNA ,  Avinash N. ANANTHAKRISHNAN

    IPC: G06F1/20 ,  G06F9/48 ,  G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F9/4843 ,  G06F9/4893 ,  Y02D10/24

    Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

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