公开(公告)号：US20180267826A1

公开(公告)日：2018-09-20

申请号：US15790444

申请日：2017-10-23

Applicant: INTEL CORPORATION

Inventor： Neven M. ABOU GAZALA ,  Paul S. DIEFENBAUGH ,  Nithyananda S. JEGANATHAN ,  Eugene GORBATOV

IPC: G06F9/46 ,  G06F12/0868

Abstract: Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.

公开(公告)号：US20180183899A1

公开(公告)日：2018-06-28

申请号：US15853624

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Nausheen ANSARI ,  Srikanth KAMBHATLA ,  Abdul R. ISMAIL ,  Karthi R. VADIVELU ,  John S. HOWARD ,  Gal YEDIDIA ,  Reuven ROZIC ,  Paul S. DIEFENBAUGH ,  Zachary F. HAMM

IPC: H04L29/06 ,  G09G3/20

CPC classification number: H04L69/03 ,  G09G3/2096 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2370/042 ,  G09G2370/047 ,  G09G2370/10 ,  G09G2370/12 ,  G09G2370/16 ,  H04L69/24 ,  H04N21/242 ,  H04N21/43635 ,  H04N21/8547

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may be operable to provide output to a unidirectional data path for carrying a packetized data stream. The second circuitry may be operable to provide output to, and obtain input from, a bidirectional control path for carrying a packetized control stream. The packetized data stream may comprise pixel data traffic and frame-synchronous metadata traffic, and the packetized control stream may comprise frame-asynchronous metadata traffic and control traffic.

公开(公告)号：US20190107879A1

公开(公告)日：2019-04-11

申请号：US16158190

申请日：2018-10-11

Applicant: INTEL CORPORATION

Inventor： Paul S. DIEFENBAUGH ,  Eugene GORBATOV ,  Andrew HENROID ,  Eric C. SAMSON ,  Barnes COOPER

IPC: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

公开(公告)号：US20170097670A1

公开(公告)日：2017-04-06

申请号：US15263274

申请日：2016-09-12

Applicant: INTEL CORPORATION

Inventor： Paul S. DIEFENBAUGH ,  Eugene GORBATOV ,  Andrew HENROID ,  Eric C. SAMSON ,  Barnes COOPER

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.