公开(公告)号：US12242859B2

公开(公告)日：2025-03-04

申请号：US17359512

申请日：2021-06-26

Applicant: INTEL CORPORATION

Inventor： Arthur Jeremy Runyan ,  Ratheesh Purushothaman Nair ,  Shailendra Singh Chauhan ,  Digant H. Solanki

IPC: G06F9/4401 ,  G06F1/3218 ,  G06F13/40

Abstract: Particular embodiments described herein provide for an electronic device that includes two or more displays and a BIOS. On startup, before the premem state and MRC initialization of the boot process, the BIOS causes power to be enabled to two or more displays. A display engine determines if a hot plug for each display is asserted and for each display where the hot plug was not asserted, the path to the display where the hot plug was not asserted is closed. In an example, the BIOS communicates the signal to power enable the first display and the second display after general-purpose input/output initialization during the boot process. After the premem stage and MRC initialization are completed, the first display and the second display are both configured to begin to display pixels.

公开(公告)号：US11043158B2

公开(公告)日：2021-06-22

申请号：US15863396

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Paul Diefenbaugh ,  Sameer Kalathil Perazhi ,  Fong-Shek Lam ,  Arthur Jeremy Runyan ,  Jason Tanner

IPC: G09G3/20 ,  G06T1/60 ,  G06F3/14 ,  G06T9/00 ,  H04N19/426

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

公开(公告)号：US11544160B2

公开(公告)日：2023-01-03

申请号：US16456403

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Bradley Coffman ,  Arthur Jeremy Runyan ,  Gustavo Patricio Espinosa ,  Daniel James Knollmueller ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/16 ,  G06F13/42 ,  G06F11/07 ,  G06F1/04

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

公开(公告)号：US10863183B2

公开(公告)日：2020-12-08

申请号：US16455540

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Arthur Jeremy Runyan

IPC: H04N19/00 ,  H04N19/172 ,  H04N19/176 ,  H04N19/119 ,  H04N19/182

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to identify a frame in a video stream, process a pixel row in the frame using a display engine to create blended and/or composited pixels, determine a coding unit (CU) row in the frame an encoder is encoding, determine if a distance between the pixel row in the frame and the CU row in the frame satisfies a threshold, and store the blended and/or composited pixels from the display engine in a cache if the threshold is satisfied or store the blended and/or composited pixels in memory if the threshold is not satisfied.

公开(公告)号：US20190320185A1

公开(公告)日：2019-10-17

申请号：US16455540

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Arthur Jeremy Runyan

IPC: H04N19/172 ,  H04N19/182 ,  H04N19/119 ,  H04N19/176

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to identify a frame in a video stream, process a pixel row in the frame using a display engine to create blended and/or composited pixels, determine a coding unit (CU) row in the frame an encoder is encoding, determine if a distance between the pixel row in the frame and the CU row in the frame satisfies a threshold, and store the blended and/or composited pixels from the display engine in a cache if the threshold is satisfied or store the blended and/or composited pixels in memory if the threshold is not satisfied.