公开(公告)号：US20160056156A1

公开(公告)日：2016-02-25

申请号：US14779936

申请日：2013-06-20

Applicant: INTEL CORPORATION

Inventor： TAHIR GHANI ,  SALMAN LATIF ,  CHANAKA D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/225 ,  H01L29/08 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Abstract translation: 描述了具有掺杂亚鳍片区域的非平面半导体器件和制造具有掺杂子鳍片区域的非平面半导体器件的方法。 例如，制造半导体结构的方法包括在半导体衬底上形成多个半导体鳍片。 固态掺杂剂源层形成在半导体衬底之上，与多个半导体鳍片保形。 在固态掺杂剂源层上形成介电层。 电介质层和固态掺杂剂源层在多个半导体鳍片的顶表面下方凹陷到大致相同的水平面，使多个半导体鳍片中的每一个的多个半导体鳍片中的每一个的突出部分暴露在多个半导体鳍片 半导体鳍片。 该方法还涉及将掺杂剂从固体掺杂剂源层驱动到多个半导体鳍片中的每一个的子鳍片区域中。