公开(公告)号：US09419212B2

公开(公告)日：2016-08-16

申请号：US14562473

申请日：2014-12-05

Applicant: INTEL CORPORATION

Inventor： Christopher W. Petz ,  Yongjun J. Hu ,  Dale W. Collins ,  Allen McTeer

IPC: H01L45/00 ,  H01L21/02 ,  H01L27/24 ,  H01L29/66

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L29/6609 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, a top electrode layer disposed on the phase-change material layer, and a barrier film comprising a group IV transition metal, a group VI transition metal, carbon (C) and nitrogen (N), the barrier film being disposed between the bottom electrode layer and the top electrode layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于相变存储器元件的阻挡膜技术和配置。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件包括底部电极层，设置在底部电极层上的选择器件层，中间电极层 配置在所述选择装置层上的相变材料层，设置在所述中间电极层上的相变材料层，配置在所述相变材料层上的上部电极层，以及包含IV族过渡金属，VI族过渡金属， 碳（C）和氮（N），阻挡膜设置在底电极层和顶电极层之间。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10347831B2

公开(公告)日：2019-07-09

申请号：US16007563

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Daniel Gealy ,  Andrea Gotti ,  Dale W. Collins ,  Swapnil A. Lengade

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.

公开(公告)号：US10008665B1

公开(公告)日：2018-06-26

申请号：US15391757

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Daniel Gealy ,  Andrea Gotti ,  Dale W. Collins ,  Swapnil A. Lengade

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.