公开(公告)号：US11018298B2

公开(公告)日：2021-05-25

申请号：US16619040

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Christopher W. Petz ,  David R. Economy

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite from the phase change material layer, a metal silicide layer (140) in contact with the metal silicon nitride layer opposite from the top electrode layer, and a conductive metal bit line (150) in contact with the metal silicide layer opposite from the metal silicon nitride layer.

公开(公告)号：US09419212B2

公开(公告)日：2016-08-16

申请号：US14562473

申请日：2014-12-05

Applicant: INTEL CORPORATION

Inventor： Christopher W. Petz ,  Yongjun J. Hu ,  Dale W. Collins ,  Allen McTeer

IPC: H01L45/00 ,  H01L21/02 ,  H01L27/24 ,  H01L29/66

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L29/6609 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, a top electrode layer disposed on the phase-change material layer, and a barrier film comprising a group IV transition metal, a group VI transition metal, carbon (C) and nitrogen (N), the barrier film being disposed between the bottom electrode layer and the top electrode layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于相变存储器元件的阻挡膜技术和配置。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件包括底部电极层，设置在底部电极层上的选择器件层，中间电极层 配置在所述选择装置层上的相变材料层，设置在所述中间电极层上的相变材料层，配置在所述相变材料层上的上部电极层，以及包含IV族过渡金属，VI族过渡金属， 碳（C）和氮（N），阻挡膜设置在底电极层和顶电极层之间。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10304749B2

公开(公告)日：2019-05-28

申请号：US15627676

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Christopher W. Petz ,  Philip M. Campbell ,  Wei Yeeng Ng ,  Kunal Bhaskar Shrotri ,  Saurabh Keshav ,  John Mark Meldrim ,  Prakash Rau Mokhna Rau ,  Tom Jibu John

IPC: H01L21/02 ,  H01L23/29 ,  H01L27/11524 ,  H01L27/1157

Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

公开(公告)号：US20180366386A1

公开(公告)日：2018-12-20

申请号：US15627676

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Christopher W. Petz ,  Philip M. Campbell ,  Wei Yeeng Ng ,  Kunal Bhaskar Shrotri ,  Saurabh Keshav ,  John Mark Meldrim ,  Prakash Rau Mokhna Rau ,  Tom Jibu John

IPC: H01L23/29 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/02

CPC classification number: H01L23/291 ,  H01L21/02145 ,  H01L21/02194 ,  H01L21/02266 ,  H01L27/11524 ,  H01L27/1157

Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.