公开(公告)号：US20180253377A1

公开(公告)日：2018-09-06

申请号：US15755414

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Cunming LIANG ,  Edwin VERPLANK ,  David E. COHEN ,  Danny ZHOU

IPC: G06F12/0802 ,  G06F21/85 ,  G06F13/20

CPC classification number: G06F12/0802 ,  G06F13/20 ,  G06F21/85 ,  G06F2213/0026

Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20210216453A1

公开(公告)日：2021-07-15

申请号：US17216462

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Cunming LIANG ,  Edwin VERPLANKE ,  David E. COHEN ,  Danny Yigang ZHOU

IPC: G06F12/0802 ,  G06F21/85 ,  G06F13/20

Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20190243757A1

公开(公告)日：2019-08-08

申请号：US16387223

申请日：2019-04-17

Applicant: Intel Corporation

Inventor： Cunming LIANG ,  Edwin VERPLANKE ,  David E. COHEN ,  Danny ZHOU

IPC: G06F12/0802 ,  G06F21/85 ,  G06F13/20

CPC classification number: G06F12/0802 ,  G06F13/20 ,  G06F21/85 ,  G06F2213/0026

Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20210203740A1

公开(公告)日：2021-07-01

申请号：US16328865

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Huawei XIE ,  Jun NAKAJIMA ,  David E. COHEN ,  Mesut A. ERGIN ,  Wei WANG

IPC: H04L29/08 ,  H04L12/861 ,  G06F9/455

Abstract: Technologies for managing paravirtual network device queue and memory of a network computing device that includes multi-core processor, a multi-layer cache, a host, and a plurality of virtual machine instances. The host is assigned a processor core of the processor and may be configured to copy a received network packet to a last level cache of the multi-layer cache and determine one or more virtual machine instances configured to process the received network packet. Each virtual machine instance has been assigned a processor core of the processor and has been allocated a first level cache of the multi-level cache memory associated with the respective processor core. The host is additionally configured to inject an interrupt into each processor core of the determined virtual machine (s) which indicates to the virtual machine instance (s) that the received network packet is available to be processed.

公开(公告)号：US20180129616A1

公开(公告)日：2018-05-10

申请号：US15573114

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Cunming LIANG ,  Danny Y. ZHOU ,  David E. COHEN ,  James R. HARRIS

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F13/1668 ,  G06F3/00 ,  G06F9/5011 ,  G06F9/5077 ,  G06F13/28 ,  G06F13/4282 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include logic to identify a Process Address Space Identifier (PASID) for a process or container of the host device and logic to associate the PASID with an individual queue pair of a hardware device of the host device, wherein the queue pair includes two complementary queues and wherein the queue pair is owned by the process or container upon association with the PASID. Other embodiments may be disclosed and/or claimed.