公开(公告)号：US09880948B2

公开(公告)日：2018-01-30

申请号：US15384203

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parthasarathy ,  David W. Burns

IPC: G06F12/14 ,  G06F12/0862

CPC classification number: G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US10678712B2

公开(公告)日：2020-06-09

申请号：US16272794

申请日：2019-02-11

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parthasarathy ,  David W. Burns

IPC: G06F12/14 ,  G06F13/42 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/0862

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US20170023994A9

公开(公告)日：2017-01-26

申请号：US13625264

申请日：2012-09-24

Applicant: Intel Corporation

Inventor： David W. Burns ,  K. S. Venkatraman

IPC: G06F9/46

CPC classification number: G06F9/3857 ,  G06F1/28 ,  G06F9/3851

Abstract: Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例，以在线程否则不能继续进行指令退休时分配线程的优先级。 对于至少一个实施例，线程是多处理器系统中的多个活动线程之一，其包括存储器活动锁定断路器逻辑和/或饥饿避免逻辑。 还描述和要求保护其他实施例。

公开(公告)号：US20190188158A1

公开(公告)日：2019-06-20

申请号：US16272794

申请日：2019-02-11

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  John W. FAISTL ,  Hermann W. GARTLER ,  Michael D. TUCKNOTT ,  Rajesh S. PARTHASARATHY ,  David W. Burns

IPC: G06F12/14 ,  G06F9/52 ,  G06F12/0842 ,  G06F12/0815 ,  G06F13/42 ,  G06F12/126 ,  G06F12/0862

CPC classification number: G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US09626194B2

公开(公告)日：2017-04-18

申请号：US13625264

申请日：2012-09-24

Applicant: Intel Corporation

Inventor： David W. Burns ,  K. S. Venkatraman

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3857 ,  G06F1/28 ,  G06F9/3851

Abstract: Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.

公开(公告)号：US10216650B2

公开(公告)日：2019-02-26

申请号：US15883021

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parthasarathy ,  David W. Burns

IPC: G06F12/14 ,  G06F13/42 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/0862

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.