公开(公告)号：US09880948B2

公开(公告)日：2018-01-30

申请号：US15384203

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parthasarathy ,  David W. Burns

IPC: G06F12/14 ,  G06F12/0862

CPC classification number: G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US10216650B2

公开(公告)日：2019-02-26

申请号：US15883021

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parthasarathy ,  David W. Burns

IPC: G06F12/14 ,  G06F13/42 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/0862

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US10678712B2

公开(公告)日：2020-06-09

申请号：US16272794

申请日：2019-02-11

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parthasarathy ,  David W. Burns

IPC: G06F12/14 ,  G06F13/42 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/0862

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US09759768B2

公开(公告)日：2017-09-12

申请号：US15249005

申请日：2016-08-26

Applicant: Intel Corporation

Inventor： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

IPC: H04L29/06 ,  G01R31/317 ,  G06F11/25 ,  G06F11/27 ,  G01R31/3177

CPC classification number: G01R31/31719 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/00 ,  G06F11/25 ,  G06F11/27

Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

公开(公告)号：US20160363624A1

公开(公告)日：2016-12-15

申请号：US15249005

申请日：2016-08-26

Applicant: Intel Corporation

Inventor： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31719 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/00 ,  G06F11/25 ,  G06F11/27

Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.