公开(公告)号：US20240020093A1

公开(公告)日：2024-01-18

申请号：US18477716

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Deepak Dasalukunte ,  Renzhi Liu ,  Hechen Wang ,  Brent Carlton

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

公开(公告)号：US20240113725A1

公开(公告)日：2024-04-04

申请号：US18539957

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: H03M1/46 ,  G11C7/16

CPC classification number: H03M1/466 ,  G11C7/16 ,  H03M1/462

Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.

公开(公告)号：US20220366968A1

公开(公告)日：2022-11-17

申请号：US17816442

申请日：2022-08-01

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G06F7/544

Abstract: Technology for generating an SRAM-based in-memory computing macro includes replacing a SRAM cell cluster defined by a generic SRAM macro with a single-bit multi-bank cluster, the single-bit multi-bank cluster including a plurality of CiM SRAM cells and a plurality of C-2C capacitor ladder cells, arranging a plurality of single-bit multi-bank clusters to form a multi-bit multi-bank cluster, and arranging a plurality of multi-bit multi-bank clusters into a multi-dimensional MAC computational unit within a region of the generic SRAM macro, where an output of at least two of the multi-bit multi-bank clusters are electrically coupled to form an output analog activation line, and where a plurality of bit lines and a plurality of word lines remain at the same grid locations as provided in the generic SRAM macro. Embodiments include arranging a plurality of multi-dimensional MAC computational units into an in-memory MAC computing array.

公开(公告)号：US11375352B2

公开(公告)日：2022-06-28

申请号：US16828986

申请日：2020-03-25

Applicant: INTEL CORPORATION

Inventor： Richard Dorrance ,  Ignacio Alvarez ,  Deepak Dasalukunte ,  S M Iftekharul Alam ,  Sridhar Sharma ,  Kathiravetpillai Sivanesan ,  David Israel Gonzalez Aguirre ,  Ranganath Krishnan ,  Satish Jha

IPC: H04W4/46 ,  G08G1/01 ,  H04W72/04

Abstract: Vehicle navigation control systems in autonomous driving rely on the accuracy of maps which include features about a vehicle's environment so that a vehicle may safely navigate through its surrounding area. Accordingly, this disclosure provides methods and devices which implement mechanisms for communicating features observed about a vehicle's environment for use in updating maps so as to provide vehicles with accurate and “real-time” features of its surroundings while taking network resources, such as available frequency-time resources, into consideration.

公开(公告)号：US20220197600A1

公开(公告)日：2022-06-23

申请号：US17131482

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  David Gonzales Aguirre

IPC: G06F7/58 ,  G06F7/483

Abstract: Techniques and mechanisms providing a mode of random number generation to satisfy a requirement for a consumer of random numbers. In an embodiment, a device comprises a Gaussian random number generator (GRNG) circuit, multiple uniform random number generator URNG circuits, and circuitry which is coupled between the GRNG circuit and the URNG circuits. Based on an indication of one or more required performance characteristics and/or one or more required statistical characteristics, a controller identifies a corresponding one of multiple available random number generation (RNG) modes. The controller communicates control signals to provide the mode with the circuitry. In another embodiment, the control signals configure the circuitry to select one or more of the URNG circuits for use in calculating random numbers with the GRNG circuit.

公开(公告)号：US12154638B2

公开(公告)日：2024-11-26

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US20240137115A1

公开(公告)日：2024-04-25

申请号：US17972965

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Sundar Krishnamurthy ,  Conor O'Keeffe ,  Deepak Dasalukunte ,  Finbarr O'Regan ,  Abhinav Vinod

IPC: H04B7/185

CPC classification number: H04B7/1855 ,  H04B7/18513 ,  H04B7/18521 ,  H04B7/18543

Abstract: An apparatus can include transceiver circuitry to receive an input signal from a target apparatus. The apparatus can further include a processing circuitry to determine position information of a source object and a target object. Based on the position information, the processing circuitry can calculate a relative velocity and determine a Doppler shift or carrier frequency offset in the input signal based on the relative velocity. The processing circuitry can adjust a local oscillator frequency based on a Doppler measured using the position information in an initial link acquisition phase. The processing circuitry can track the Doppler continuously over a range of tens of gigahertz accounting for Doppler phase ambiguities, and correct for a tracked Doppler shift by partially adjusting a local oscillator frequency and by correcting a residual Doppler shift digitally.

公开(公告)号：US20230251943A1

公开(公告)日：2023-08-10

申请号：US18298906

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Renzhi Liu ,  Hechen Wang ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F11/20

CPC classification number: G06F11/2041

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

公开(公告)号：US11597393B2

公开(公告)日：2023-03-07

申请号：US16830349

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Ignacio Alvarez ,  Maria Soledad Elli ,  Sridhar Sharma ,  Satish Jha ,  Kathiravetpillai Sivanesan ,  S M Iftekharul Alam

IPC: B60W40/04 ,  B60W60/00 ,  G08G1/0969 ,  G08G1/0967 ,  B60W50/00

Abstract: According to various embodiments, a method for operating a vehicle may include determining a vehicular area having traffic conditions or characteristics different from traffic conditions of a current or previous location of the vehicle; obtaining traffic and driving information for the determined vehicular region; changing or updating one or more of driving model parameters of a safety driving model during operation of the vehicle based on the obtained traffic and driving information; and controlling the vehicle to operate in accordance with the safety driving model using the one or more changed or updated driving model parameters. A vehicle may seamlessly update operational rules and/or handover of traffic and driving information for transitioning from one region to another.

公开(公告)号：US20220334801A1

公开(公告)日：2022-10-20

申请号：US17855097

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Shigeki Tomishima

IPC: G06F7/523 ,  G06F7/50

Abstract: Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.