公开(公告)号：US20240020093A1

公开(公告)日：2024-01-18

申请号：US18477716

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Deepak Dasalukunte ,  Renzhi Liu ,  Hechen Wang ,  Brent Carlton

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

公开(公告)号：US12154638B2

公开(公告)日：2024-11-26

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US20230251943A1

公开(公告)日：2023-08-10

申请号：US18298906

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Renzhi Liu ,  Hechen Wang ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F11/20

CPC classification number: G06F11/2041

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

公开(公告)号：US11597393B2

公开(公告)日：2023-03-07

申请号：US16830349

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Ignacio Alvarez ,  Maria Soledad Elli ,  Sridhar Sharma ,  Satish Jha ,  Kathiravetpillai Sivanesan ,  S M Iftekharul Alam

IPC: B60W40/04 ,  B60W60/00 ,  G08G1/0969 ,  G08G1/0967 ,  B60W50/00

Abstract: According to various embodiments, a method for operating a vehicle may include determining a vehicular area having traffic conditions or characteristics different from traffic conditions of a current or previous location of the vehicle; obtaining traffic and driving information for the determined vehicular region; changing or updating one or more of driving model parameters of a safety driving model during operation of the vehicle based on the obtained traffic and driving information; and controlling the vehicle to operate in accordance with the safety driving model using the one or more changed or updated driving model parameters. A vehicle may seamlessly update operational rules and/or handover of traffic and driving information for transitioning from one region to another.

公开(公告)号：US20220334801A1

公开(公告)日：2022-10-20

申请号：US17855097

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Shigeki Tomishima

IPC: G06F7/523 ,  G06F7/50

Abstract: Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.

公开(公告)号：US20220012016A1

公开(公告)日：2022-01-13

申请号：US17485179

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G06F7/544 ,  G06F7/523 ,  G06N3/04 ,  H03M1/78 ,  H03M1/80

Abstract: Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

公开(公告)号：US11205749B2

公开(公告)日：2021-12-21

申请号：US16474575

申请日：2017-03-23

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Farhana Sheikh

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H04L5/14 ,  H01L43/10

Abstract: A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.

公开(公告)号：US09967820B2

公开(公告)日：2018-05-08

申请号：US15196070

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Minyoung Park ,  Alexander W. Min ,  Farhana Sheikh

IPC: H04W72/04 ,  H04W52/02 ,  H04L29/06

CPC classification number: H04W52/0229 ,  H04L1/00 ,  H04L1/0061 ,  H04L12/12 ,  H04L27/06 ,  H04L69/22 ,  Y02D70/00

Abstract: According to the present disclosure, a communication device configured to power on a main receiver to receive data from a network includes: a low power receiver configured to receive a wake up packet, including a preamble, from the network and oversample the wake up packet; a circuit arrangement including: a correlator configured to correlate the oversampled portion of the preamble; a delay and adder configured to take an output of the correlator, delay the output of the correlator, and add the output of the correlator back onto itself to produce a delay output; a peak detector configured to detect a peak pattern in the delay output; a demodulator configured to calculate a decoding threshold value to produce a demodulated data; and a packet parser configured to check the demodulated data for a data set in order to selectively output a nonzero signal to power on the main receiver.

公开(公告)号：US20240396568A1

公开(公告)日：2024-11-28

申请号：US18792714

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Brent Carlton

IPC: H03M1/14 ,  G06F7/544 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for technology including a digital to analog conversion (DAC) stage to generate analog input activation signals, a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage, an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results, and analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage, and a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.

公开(公告)号：US20240113725A1

公开(公告)日：2024-04-04

申请号：US18539957

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: H03M1/46 ,  G11C7/16

CPC classification number: H03M1/466 ,  G11C7/16 ,  H03M1/462

Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.