公开(公告)号：US20160093540A1

公开(公告)日：2016-03-31

申请号：US14499120

申请日：2014-09-27

Applicant: INTEL CORPORATION

Inventor： Shuhong LIU ,  Nilanjan Z. GHOSH ,  Zhiyong WANG ,  Deepak GOYAL ,  Shripad GOKHALE ,  Jieping ZHANG

IPC: H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  G01B11/06

CPC classification number: H01L22/12 ,  G01B11/06 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2224/81

Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.

Abstract translation: 一种包括在成型材料层从光源发射太赫兹光束的方法; 检测光束的反射率; 并确定成型材料层的厚度。 一种包括面板支撑件的系统，其可操作以支撑包括布置在平面阵列中的多个基板的面板; 光源，其可操作以在所述面板支撑件上的面板处发射太赫兹光束; 检测器，用于检测在面板上发射的太赫兹波束的反射; 以及处理器，其可操作以基于由检测器检测的发射的太赫兹光束的时间延迟来确定面板上的材料的厚度。

公开(公告)号：US20210193552A1

公开(公告)日：2021-06-24

申请号：US16721809

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Jin YANG ,  Chia-Pin CHIU ,  Peng LI ,  Deepak GOYAL

IPC: H01L23/367 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

公开(公告)号：US20220199482A1

公开(公告)日：2022-06-23

申请号：US17131671

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Zhimin WAN ,  Peng LI ,  Deepak GOYAL

IPC: H01L23/367 ,  H01L23/40 ,  H01L23/38

Abstract: Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.

公开(公告)号：US20200098554A1

公开(公告)日：2020-03-26

申请号：US16481056

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Purushotham Kaushik MUTHUR SRINATH ,  Richard Kenneth BREWER ,  Deepak GOYAL

IPC: H01L21/027 ,  H01L21/265 ,  H01J37/31

Abstract: Systems and methods of sample preparation using dual ion beam trenching are described. In an example, an inside of a semiconductor package is non-destructively imaged to determine a region of interest (ROI). A mask is positioned over the semiconductor package, and a mask window is aligned with the ROI. A first ion beam and a second ion beam are swept, simultaneously or sequentially, along an edge of the mask window to trench the semiconductor package and to expose the ROI for analysis.