公开(公告)号：US20190103690A1

公开(公告)日：2019-04-04

申请号：US15721546

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Xiang LI ,  George VERGIS ,  Douglas HEYMANN

IPC: H01R12/73 ,  H01R12/72 ,  H01R12/83 ,  H05K1/02

Abstract: Embodiments include devices, systems, and methods relating to removing heat from a memory module in a connector. One embodiment relates to a memory module connector comprising a first arm, a second arm, and a body portion positioned between the first arm and the second arm, the body portion configured to accept a memory module therein. The memory module connector includes a structure coupled to the first arm and configured to be electrically coupled to a printed circuit board. The memory module connector also includes a heat spreader coupled to the first arm, the heat spreader configured to be brought into thermal contact with a memory module component. Other embodiments are described and claimed.

公开(公告)号：US20240397628A1

公开(公告)日：2024-11-28

申请号：US18797211

申请日：2024-08-07

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Douglas HEYMANN ,  Xiang LI ,  Ariadna HERNANDEZ VAZQUEZ

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11

Abstract: Apparatus and methods for conductive memory module notch and connector-to-motherboard pins for power or ground. A memory module includes a conductive notch that is coupled to either one or more ground planes in respective layers in the memory module's PCB or to a power rail formed on one or more layers in the PCB. A memory module connector includes a notch pin that is configured to mate with the conductive notch when the memory module is installed in the connector. The connector is mounted to a motherboard or the like and the notch pin is coupled to either power (e.g., Vin) or ground in the motherboard. When coupled to power, Vin is supplied to the memory module via the notch pin/conductive notch. When coupled to ground on the motherboard, at least a portion of the ground planes in the PCB are coupled to ground via the notch pin/conductive notch.

公开(公告)号：US20240364037A1

公开(公告)日：2024-10-31

申请号：US18768742

申请日：2024-07-10

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Douglas HEYMANN ,  John R. DREW ,  Xiang LI

IPC: H01R13/24

CPC classification number: H01R13/2478

Abstract: Compression Attached Memory Module (CAMM) connector pin with multi-spring (dual bend direction) levers and associated connectors. The connector pin comprises an upper cantilevered spring member coupled to an upper portion of a body and a lower cantilevered spring member coupled to a lower portion of the body. Each of the upper and lower cantilevered spring members include at least one forward bending lever and a backward bending lever. The upper cantilevered spring member may have a pair of arms merging to form an upper unified spring member having a nose and looping backwards over the arms and having an apex. A lower cantilevered spring may have a pair of legs merging to form a lower unified spring member having a nose and looping backwards under the legs and having a bottom. When compressed the forward and backward bending levers counteract one another in the horizontal plane, reducing horizontal displacement.

公开(公告)号：US20210407553A1

公开(公告)日：2021-12-30

申请号：US17369851

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  George VERGIS

IPC: G11C5/14 ,  G05F1/46

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) to generate a supply voltage for a memory module. The PMIC is to perform a measurement during bring-up of the memory module of a worst case current draw of the memory module and/or corresponding droop in the supply voltage. The PMIC is to apply a step-up to the supply voltage in accordance with the measurement in response to detection by the PMIC of a surge in the memory module's current draw during operation of the memory module.

公开(公告)号：US20240407127A1

公开(公告)日：2024-12-05

申请号：US18805225

申请日：2024-08-14

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  Debra BEYER ,  Ameya LIMAYE ,  Mark MACDONALD ,  Sung Ki KIM

IPC: H05K7/20

Abstract: A cooling system includes a cooling fluid bypass to direct cooling fluid around a processor device to a memory module shadowed by the processor device from the cooling fluid flow. The fluid bypass allows the system to direct cooling fluid to the shadowed memory module that has not been used to cool the processor. There are various configurations, allowing the bypassing of different amounts of cooling fluid, allowing system designers to balance a tradeoff between processor heat and memory module heat.

公开(公告)号：US20220418145A1

公开(公告)日：2022-12-29

申请号：US17898323

申请日：2022-08-29

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  George VERGIS

IPC: H05K7/14

Abstract: A server memory device provides highspeed storage to a computer system. The server memory device has a connector that can make electrical coupling with the computer system. The server memory device includes two memory modules, each with one or more memory chips. Each memory module is coupled and bonded with an interposer. Each interposer is coupled and bonded with the server memory device connector. The connector and interposers provide a high-density interconnect that connects two memory modules to a computer system. The server memory device has a form factor that uses a single unit (1U) of a server rack, doubling the memory capacity provided to the computer system through a single unit (1U) equipment rack.

公开(公告)号：US20200027500A1

公开(公告)日：2020-01-23

申请号：US16584724

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  Wei P. CHEN ,  Suresh CHITTOR ,  George VERGIS

IPC: G11C11/406 ,  G06F13/16 ,  G01K13/00

Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.