公开(公告)号：US20240421516A1

公开(公告)日：2024-12-19

申请号：US18821088

申请日：2024-08-30

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R12/70 ,  H01R13/20 ,  H05K1/11

Abstract: Examples include techniques for a module connector design to improve pin connection. The techniques include covering top and bottom cavities of a connector that includes connector pins arranged to be coupled with a printed circuit board via a reflow soldering process to prevent a film from forming on the connector pins during or after the reflow soldering process.

公开(公告)号：US20230229606A1

公开(公告)日：2023-07-20

申请号：US18123218

申请日：2023-03-17

Applicant: Intel Corporation

Inventor： George VERGIS

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4282

Abstract: A memory module management controller in a memory module includes a reset controller that monitors a reset signal received from a host memory controller in the host system that is communicatively coupled to the memory module. The memory module management controller includes sideband bus control circuitry. The memory module also includes memory integrated circuits (for example, Dynamic Random Access Memory (DRAM)) and a Registering Clock Driver (RCD). The reset signal from the host memory controller can be time multiplexed, a short duration pulse to indicate reset of the sideband bus control circuitry and a long duration pulse to indicate reset of other components in the memory module, for example, memory integrated circuits and/or Registering Clock Driver (RCD).

公开(公告)号：US20230005882A1

公开(公告)日：2023-01-05

申请号：US17902740

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： George VERGIS ,  Min Suet LIM ,  Luis Carlos ALVAREZ MATA ,  Ankita TIWARI ,  Xiang LI

IPC: H01L25/065 ,  H01L23/40 ,  H01L25/18 ,  H01R12/71 ,  H01R13/24 ,  H01L23/50

Abstract: Memory on Package (MOP) apparatus with reverse CAMM (Compression Attached Memory Module) and compression mount technology (CMT) connector(s). The MOP includes a first (MOP) substrate to which one or more CPUs, SoC, and XPUs that is operatively coupled to one or more CAMMs with a CMT connector(s) disposed between an array of CMT contact pads on the CAMM substrate and an array of CMT contact pad on the substrate. The one or more CAMMs are include multiple memory chips or packages such as LP DDR chips or DDR (S)DRAM chips/packages mounted to an underside of the CAMM substrate via signal coupling means such as a ball grid array (BGA), where the CAMM orientation is inverted such that the memory chips/packages are disposed downward, resulting in a reduced Z-height of the MOP. A MOP may include two CAMMs with a respective CMT connector disposed between the CAMM substrates and the MOP substrate.

公开(公告)号：US20220361328A1

公开(公告)日：2022-11-10

申请号：US17871686

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H05K1/11 ,  H05K1/18 ,  G06F1/18

Abstract: Power conversion modules using compression mount technology (CMT) connectors and associated apparatus and methods. Assemblies include a CMT connector that includes an array of spring-loaded CMT pins or contacts that are configured to contact respective pads on a pair of printed circuit board (PCBs), such as for VR module card or power conversion module and a motherboard. The power conversion modules in combination with the CMT connectors provide several advantages, including, a common VR module/power conversion module/motherboard footprint across OEM platforms and test hardware, just in time VR module attachment for improved inventory management, removable power delivery solution makes the platform more conducive to debug, in field servicing, and platform upgradable for higher power CPU/GPU/XPU.

公开(公告)号：US20210407553A1

公开(公告)日：2021-12-30

申请号：US17369851

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  George VERGIS

IPC: G11C5/14 ,  G05F1/46

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) to generate a supply voltage for a memory module. The PMIC is to perform a measurement during bring-up of the memory module of a worst case current draw of the memory module and/or corresponding droop in the supply voltage. The PMIC is to apply a step-up to the supply voltage in accordance with the measurement in response to detection by the PMIC of a surge in the memory module's current draw during operation of the memory module.

公开(公告)号：US20210336767A1

公开(公告)日：2021-10-28

申请号：US17359152

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Raghunandan MAKARAM ,  Kirk S. YAP ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE ,  Jacob DOWECK

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  G11C29/42 ,  G11C29/12

Abstract: A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.

公开(公告)号：US20210183410A1

公开(公告)日：2021-06-17

申请号：US17132504

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  Konika GANGULY

IPC: G11C5/04 ,  G11C5/06 ,  H01L23/00 ,  H01L23/538

Abstract: An apparatus is described. The apparatus includes a module to plug-into a printed circuit board. The module has a connector along a center axis of the module. The module further has a first semiconductor chip disposed in a first region of the module that resides between an edge of the module and a side of the connector. The module has a second semiconductor chip disposed in a second region of the module that resides between an opposite edge of the module and an opposite side of the connector.

公开(公告)号：US20190102331A1

公开(公告)日：2019-04-04

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang LI ,  Yunhui CHU ,  Jun LIAO ,  George VERGIS ,  James A. McCALL ,  Charles C. PHARES ,  Konika GANGULY ,  Qin LI

IPC: G06F13/16 ,  G11C5/06 ,  G11C5/04 ,  G06F1/18 ,  H01R12/73

CPC classification number: G06F13/1694 ,  G06F1/185 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  H01R12/73

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US20190042499A1

公开(公告)日：2019-02-07

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

公开(公告)号：US20190042095A1

公开(公告)日：2019-02-07

申请号：US16111156

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： George VERGIS ,  Bill NALE ,  Derek A. THOMPSON ,  James A. McCALL ,  Rajat AGARWAL ,  Wei P. CHEN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a memory controller having register space to inform the memory controller that the memory controller is coupled to a memory module that conforms to a first memory chip industry standard specification but is composed of memory chips that conform to a second, different memory chip industry standard specification.